“Developing heterogeneous systems (CPU plus FPGA) using the OpenCL standard”

On Nov. 15, 2011, Altera Corporation announced a development program focused on the Open Computing Language (OpenCL™) standard for FPGAs and SoC FPGAs. Altera's OpenCL program combines the parallel performance capability of FPGAs with the OpenCL standard to enable powerful system acceleration.

Through its OpenCL program, Altera has engaged with multiple customers and expanded its university program to support the OpenCL standard for FPGA development in academia, and is actively contributing to the evolution of the OpenCL standard based on customer feedback.

Read more: Altera Announces Industry's First OpenCL Program for FPGAs

To learn more about OpenCL - The Open Standard for Parallel Programming of Heterogeneous Systems, visit the KHRONOS Group Website

Keynote Talk

• Prof. Stephen Brown, Towards OpenCL Compilation into High-Performance Hardware for FPGAs. University of Toronto, Canada

Invited Talk

• Dr. Pascal Benoit, Distributed Approaches for Self-Adaptive Embedded Systems. Electrical Engineering department of University of Montpellier, France

Distinguished Talk

• A Configurable VHDL Template for Parallelization of 3D Stencil Codes on FPGAs.
  Prof. Franz Richter, Michael Schmidt and Dietmar Fey, FAU Erlangen-Nuremberg, Germany

Industrial Talk

• From Streaming Models to FPGA Implementations.
  Hugo Andrade, Jeff Correll, Amal Ekbal, Arkadeb Ghosal, Douglas Kim, Jacob Kornerup, Rhishikesh Limaye, Ankita Prasad, Kaushik Ravindran, Trung N Tran, Mike Trimborn, Gerald Wang, Ian Wong, Guang Yang , National Instruments Corporation, USA

Regular Talks

• Identifying Data-Dependent System Scenarios in a Dynamic Embedded System.
  Elena Hammari*, Francky Catthoor**, Per Gunnar Kjeldsberg*, Jos Huisken***, Konstantinos Tsakalis****, Leonidas Iasemidis**** ,
  * Norwegian University of Science and Technology, Norway
  ** Imec and K.U.Leuven, Belgium
  *** Imec / Holst Centre, The Netherlands
  **** Arizona State University, USA
• Generic Synthesizable Hardware Platform for Multicore Architectures.
  Natwar Agrawal, Annie Avakian, Ranga Vemuri , University of Cincinnati, USA

Panel Discussion Session

Chair: TBA

Visit High Level Design for FPGAs Panel

“Hardware security and trust in reconfigurable heterogeneous systems”

A wide range of applications relies on dedicated, embedded hardware platforms, which, in a most complex case, tend to be reconfigurable heterogeneous systems. The critical issue is the trusted and secure hardware design. The other critical issue is the intellectual-property protection.

The applications may range from Internet protocols, telecommunication systems, power grids, military systems, databases, and financial services, if to list some of these.

We will concentrate, but not limiting, on the following topics.

• Design methodologies for secure and trusted hardware and software
• Protection and identification techniques for IP cores
• Trojan detection and hardware cryptography

Industrial Keynote Talk

• Jonathan P. Graf, Ensuring Design Integrity through Analysis of FPGA Bitstreams and IP Cores. Luna Innovations Inc., USA

Invited talk

• Dr. Yohei Hori, Tackling the Security Issues of FPGA Partial Reconfiguration with Physical Unclonable Function. National Institute of Advanced Science and Technology, Japan

Regular talks

• Cryptanalysis on Reconfigurable Computers.
  Prof. Tim Güneysu, Horst Goertz Institute for IT-Security, Ruhr-Universitaet Bochum, Germany
• A Practical FPGA Implementation of Regular Expression Matching with Look-ahead Assertion.
  Yoichi Wakaba, Masato Inagi, Shin'ichi Wakabayashi, Hiroshima City University, Japan
• Watermarking-Based Protection of Embedded Cores on FPL Devices.
  L. Parrilla*, E. Castillo*, A. García*, G. Botella**,
  * Dept. Electronics and Computer Technology, University of Granada, Granada, Spain
  ** Dept. of Computer Architecture and Automation, Complutense University of Madrid, Madrid, Spain

Panel Discussion Session

Chair: TBA

Visit Hardware Security Panel

Visit also ERSA’11 security related sessions.

ERSA’11 Keynote talks:

• Prof. Eugene Howard Spafford, The Nature of Cyber Security.
• Prof. Jürgen Teich, Verifying the Authorship of Embedded IP Cores: Watermarking and Core Identification Techniques.

ERSA’11 Invited talks:

• Dr. Kimmo Järvinen, Elliptic curve cryptography on FPGAs: How fast can we go with a single chip?
• Prof. Ryan Kastner, Enforcing Information Flow Guarantees in Reconfigurable Systems with Mix-trusted IP.
• Dr. Ted Huffmire, 3-D Extensions for Trustworthy Systems.
• Dr. Steve Borbash, It Takes a “Village” (to create a science): From crypto science to security science.
• And much more

For full list of presentations download the ERSA13 Schedule in pdf format

“Best Young Entrepreneur”

• Ahmed Hassan, Mohammed Gouda,
  Kashef, Egypt, iITC, Sweden
  “Bastet” Subsurface Detection Air Vehicle
• Manal K. Jalloul 
  American University of Beirut, Lebanon
  A Novel Parallel Computing Approach for Motion Estimation Based on Particle Swarm Optimization

• Addressing the Challenges of Hardware Assurance in Reconfigurable Systems
  William H. Robinson, Trey Reece, Nihaar N. Mahatmem
  Vanderbilt University, Nashville, TN, USA

Communication Techniques in ReconFigurable Systems
Chair: Qian Zhao, Kumamoto University, Japan

• An Area-Efficient Asynchronous FPGA Architecture for Handshake-Component-Based Design
  Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
  Tohoku University, Japan
• Implementing Alamouting 2x1 Transmit Diversity on Software Defined Radios
  Anaam Ansari and Robert Morelos Zaragoza
  San Jose State University, California, USA

Developing Reconfigurable Heterogeneous Systems
Chair: Prof. William H Robinson, Vanderbilt Univ. USA

• Heuristically Driven Task Agglomeration in Limited Resource Partially Reconfigurable Systems
  David Austin and B. Earl Wells
  University of Alabama in Huntsville, Alabama, USA
• An Automatic Design and Implementation Framework for Reconfigurable Logic IP Core
  Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, and Toshinori Sueyoshi
  Graduate School of Science and Technology, Kumamoto University, Japan