"Von Neumann's architecture lasted for 75 years.
That genius can no longer lead us into the new age of computing that is upon us.
This competition seeks to acknowledge those pioneers that are helping to build the new computing landscape"
Manal Jalloul was born in 1984 in Beirut , Lebanon. She received her BE in Electrical and Communication Engineering from Beirut Arab university, Beirut, Lebanon in 2007, and her ME from the American University of Beirut in 2009. She is the recipient of Jamal Abdul Nasser Award for Academic Excellence from Beirut Arab University in 2007.She is currently pursuing her PhD in Electrical and Communication Engineering under the supervision of Prof. Mohammad Adnan Al-Alaoui at the American University of Beirut.
Her research interests lie in the field of video and image processing, filter design, and parallel programming. She has published papers in these areas in peer reviewed conferences. She has been working as a Graduate Research Assistant (GRA) in AUB since 2007. She is a member of the Digital Signal Processing and Adaptive Filtering group at AUB(DSAF) ) and of the CUDA teaching Center at AUB. Part of her duties as a GRA included teaching several courses and labs including Digital Image Processing Lab, CUDA lab, Digital Signal Processing Lab, and C++ Programming Lab.
Today, we witness a high revolution in the hardware industry. There is a transition to multi-core and many-core systems which require a change in the programming approach to develop algorithms with high parallelism in order to take advantage of the high speedup provided by the available hardware. Existing ME algorithms are serial. They operate on blocks of the frame serially following the raster order. The proposed algorithm, on the other hand, exhibits high level of data parallelism. It performs motion estimation for all blocks of the frame in parallel. As a result, the proposed algorithm provides tremendous speedup and improved quality as compared to the exhaustive-search algorithm and to the well-known fast searching techniques.The proposed scheme will be implemented on the massively parallel architecture of the GPU using the NVIDIA CUDA platform and evaluated.
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