ERSA’11: Engineering of Reconfigurable Systems and Algorithms

alert

Please note that ERSA has bit different regulations than WorldComp

alert SLIDES ARE AVAILABLE

Prof David Lorge Parnas  
How Engineering Mathematics can Improve Software

ERSA Scope

The international conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) was founded in 2001 and, since then, has been held each year in Las Vegas.

ERSA conference solicits papers from all aspects of reconfigurable computing, including classical programmable logic, as well as reconfigurable multiprocessing related papers. The range of topics covers theory, architecture, algorithms, design systems, and applications that demonstrate the benefits of reconfigurable computing:

  • Theory - Synthesis, Mapping, Parallelization, Partitioning...
  • Software - CAD, Languages, Compilers, Operating Systems...
  • Hardware - Adaptive and Dynamic Hardware, Reconfigurable Architectures...
  • Applications - Mobile Computing, Automotive Industry, Smart Cameras...

ERSA conference explores emerging trends and novel ideas in the area of parallel, reconfigurable, high-performance computing architecture, design methods and applications. ERSA is promoting multidisciplinary research and new visionary approaches including bio-inspired architectures, computational biology, physics etc.

ERSA conference brings together leading scientists and researchers from academia and industry. The best papers of ERSA have been published as the special issues of top archival journals.

All conference proceedings/books are considered for inclusion in major database indexes.

Topics, Sessions, and Partnerships

Hot Topics

This year, ERSA is particularly interested in the topics listed below. We will arrange several specialized sessions under these topics and encourage authors to submit their papers for these topics.

  • Formal Methods and Engineering: Tools and Theory of Design Methods
  • Reconfigurable and Evolvable Hardware Architectures: Bio-Inspired, Low-Power, Multi-Core, Achronix, NuFPGA, etc.
  • Security: Threats and Solutions for Reconfigurable Embedded Systems

Certainly, we welcome all papers submitted under other topics too.

The best papers will be published after conference in “The Journal of Supercomputing”, Springer.

Types of Sessions

ERSA conference is composed of research presentations, keynote lectures, invited presentations, tutorials, panel discussions, and poster presentations.

This year, ERSA will have the following types of dedicated sessions:

  • Specialized Research Sessions
    The session is devoted for an academic research on a specific topic; as, for example "Partial Reconfiguration", "Reconfigurable Supercomputing", etc. Papers in this session are not close to each other, do not necessarily use similar approaches to solve the problems; moreover, the approaches (papers) may compete with each other.
  • Research Project Sessions
    The session is devoted for a specific academic research projects or a bunch of projects with a similar approach; curried out by leading research team(s) and/or lab(s), (may be by several universities), and receiving external funding. For example, EU projects are welcome, and projects funded by national science funds. Thus, papers in this session are close to each other forming an integral approach to solve a complex technical problem, i.e. forming a project.
  • Industrial Sessions
    This session is devoted for industrial/commercial solutions, design methods, and products. Leading, established companies, as well as start-ups, may present their solutions and approaches.
  • Panel Sessions
    The aim of panel sessions is to carry out a discussion among panellists and attendees about most intriguing, provocative, and important topics.
  • Tutorials
    Industrial and/or academic partners may present a full coverage of a proposed topic; about their commercial products, academic approaches etc. In addition, overview type Tutorials is welcome.
  • Demos/Exhibitions
    Industrial and/or academic partners present design systems, products etc.

Proposals for Sessions

In several cases, ERSA conference invites outstanding researcher to arrange a session. In addition, authors can submit proposals for organizing a session in each category.

  • Specialized Research Sessions: The deadline for proposals is January 15, 2011. If the proposal is approved, the session chairs can call invited speakers. In addition, they advertise the open submission of regular papers. For more details, please visit section "Submission".
  • Research Project Sessions: The deadline for proposals is March 1, 2011. If you consider submitting a proposal, please take contact with ERSA org committee as soon as possible. This helps to plan and organize the conference. If the proposal is approved, the session and accepted papers are considered as "Invited". Otherwise, the authors can resubmit the session and papers as "Regular". In this case, all papers will be reviewed in a regular way, after which the decision about acceptance will be made. In addition, authors may submit a bunch of papers for regular papers' deadline for considering as a "Regular Research Project Session". Again, all papers will be reviewed in a regular way.
  • For all other sessions, ERSA accepts proposals until regular papers' "Notification".

If you have any questions about organizing Sessions at ERSA conference, please contact the ERSA Chair.

Industrial Partnership Programme

The ERSA conference is a part of federated congress, WORLDCOMP, of more than 20 conferences, which brings together more than 2000 participants around the world. WORLDCOMP covers all aspects of computer science, engineering, and applications.

At WORLDCOMP, there is a cluster of closely related conferences with mutual interests. This cluster forms an area of hardware design, reconfigurable computing systems and hardware, embedded systems, application specific systems, signal and image processing, and parallel, high-performance computing. We estimate that there are about 300-400 attendees who are interested in this cluster. We anticipate that ERSA'11 will have around 70 attendees.

The ERSA conference would be a good opportunity to show your products to the conference and at the same time, your company and our delegates would benefit from it.

Standard levels of sponsorship

There are five levels of sponsorship, staring with bronze level and including a table + elec outlet + the opportunity to demo (if you like) your product to the attendees of ERSA and WORLCOMP; around 2000 attendees.

Tailored offers for partners

There are several offers for industrial partners, which highly depend on size, format, and individual agreements.

  • Industrial Sessions: Industrial partners can arrange sessions to present their technical solutions, design methods, and products; deliver talks and demos. The offer depends on the actual content of session.
  • Special promoting: On a higher level of sponsorship (Gold level and above) you can arrange sponsored:
    • Coffee Breaks with specific Advertising,
    • Conference Bags with special Promotional Items,
    • ERSA T-Shirts with companies’ logos

    You can use these three options if, for example, you do not plan to send someone to conference but you require a higher level of visibility.

For more info, contact the ERSA PC at inf@ersaconf.org.


Founder and Chair of ERSA Conference

Dr Toomas P Plaks
London

Recipients of ERSA - WORLDCOMP 2011 Awards

OUTSTANDING ACHIEVEMENT AWARD

Prof. David Lorge Parnas Prof. David Lorge Parnas

Middle Road Software, Inc, Canada

Dr.h.c.: ETH Zürich, Louvain, Lugano
Fellow: RSC, ACM, CAE, GI, IEEE; MRIA
Professor Emeritus, CAS, Engineering, McMaster University
Hamilton, Ontario, Canada
Professor Emeritus, CSIS, University of Limerick
Limerick, Ireland

OUTSTANDING ACHIEVEMENT AWARD

Prof. Eugene Howard Spafford Prof. Eugene Howard Spafford

Purdue University, USA

Executive Director,
CERIAS (Center for Education and Research in Information Assurance and Security)
Purdue University, West Lafayette, Indiana, CERIAS, USA


alert

This part is under re-construction to fit the final program

ERSA’11 KEYNOTE TALKS

ERSA/WORLDCOMP KEYNOTES

Prof. David Lorge Parnas, "How Engineering Mathematics can Improve Software"

ERSA/WORLDCOMP KEYNOTE TALK

Professor David Lorge Parnas
How Engineering Mathematics can Improve Software,
Prof. David Lorge Parnas,
Middle Road Software, Inc, Canada
Time: 08:50 - 09:45am
Location: Lance Burton Theater
Prof. David Lorge Parnas, Ph.D., P.Eng. (Ontario)
Dr.h.c.: ETH Zürich, Louvain, Lugano
Fellow: RSC, ACM, CAE, GI, IEEE; MRIA
Professor Emeritus, CAS, Engineering, McMaster University
Hamilton, Ontario, Canada
Professor Emeritus, CSIS, University of Limerick
Limerick, Ireland

Abstract

For many decades we have been promised that the “Formal Methods” developed by computer scientists would bring about a drastic improvement in the quality and cost of software development. That improvement has not materialized. ...

Bio

Dr David Lorge Parnas has been studying industrial software development since 1969. Many of his papers have been found to have lasting value. For example, a paper written 25 years ago, based on a study of avionics software, was recently awarded a SIGSOFT IMPACT award.


SLIDES: "How Engineering Mathematics can Improve Software"

Prof. Eugene Howard Spafford, "The Nature of Cyber Security"

ERSA/WORLDCOMP KEYNOTE TALK

Prof. Eugene Howard Spafford
The Nature of Cyber Security,
Prof. Eugene Howard Spafford,
Purdue University, USA
Leading computer security expert
Time: 09:50 - 10:45am
Location: Lance Burton Theater

Abstract:

There is an on-going discussion about establishing a scientific basis for cyber security. Efforts to date have often been ad hoc and conducted without ...

Bio:

Eugene Howard Spafford is a Professor in the Purdue University. He is historically significant Internet figure, he is renowned for first analyzing the Morris Worm, one of the earliest computer worms, ...

ERSA KEYNOTES

Prof. Jürgen Teich, "Verifying the Authorship of Embedded IP Cores:..."

Prof. Jürgen Teich
Verifying the Authorship of Embedded IP Cores: Watermarking and Core Identification Techniques,
Prof. Jürgen Teich and Dr. Daniel Ziener,
University of Erlangen-Nuremberg, Germany
Time: 10:40am - 11:10am
Location: Gold Room

Abstract:

In this paper, we present an overview of new watermarking and identification techniques for FPGA IP cores. Unlike most existing watermarking techniques, the focus of our techniques lies on ease of verification, ...

Bio:

Jürgen Teich received his masters degree (Dipl.-Ing.) in 1989 from the University of Kaiserslautern (with honours). From 1989 to 1993, he was PhD student at the University of Saarland, Saarbruecken, Germany from where he received his PhD degree (summa cum laude). ...

Prof. Shiu-Kai Chin, "Logic Design for Access Control,..."

Prof. Shiu-Kai Chin
Logic Design for Access Control, Security, Trust, and Assurance,
Prof. Shiu-Kai Chin,
Syracuse University, USA
Senior Scientist, Serco-NA, Inc.
Time: 11:20am - 11:50am
Location: Gold Room

Abstract:

Designers of hardware and software are frequently doing their work as part of larger systems where the confidentiality, integrity, and availability of information and other resources is a primary concern. Whether the system is a military one where assurance of mission critical capabilities is paramount, ...

Bio:

Shiu-Kai Chin is a Professor in the Department of Electrical Engineering and Computer Science at Syracuse University, Syracuse, New York. His research applies mathematical logic to the engineering of trustworthy systems. ...

Prof. Cynthia Irvine, "Grounding Trust"

Prof. Cynthia Irvine
Grounding Trust
Prof. Cynthia Irvine,
Naval Postgraduate School, USA
Time: 11:50am - 12:20pm
Location: Gold Room

Abstract:

The word “security” is often defined as “the freedom from danger” or “the freedom from doubt and fear.” Life is dangerous, ...

Bio:

Dr. Cynthia Irvine is the Director of the Center for Information Systems Security Studies and Research (CISR) and a Professor of Computer Science at the Naval Postgraduate School, ...

Prof. Dominique Lavenier, "Next Generation Sequencing ..."

Prof. Dominique Lavenier
Next Generation Sequencing Data Processing
How reconfigurable computing can help?,
Prof. Dominique Lavenier,
IRISA, Rennes, France
Time: 02:30pm - 03:00pm
Location: Gold Room

Abstract:

With the fast progress of next generation sequencing (NGS) machines, genomics research is currently strongly shaken. These new biotechnologies generate impressive flow of raw genomic data from which pertinent and significant information must be extracted. ...

Bio:

Dominique Lavenier is a senior CNRS (French National Center for Scientific Research) researcher and Professor at ENS Cachan. He is currently leading the Symbiose bioinformatics research group at IRISA. ...

Prof. Andy Tyrrell, "Reconfigurable and Evolvable Architectures ..."

Prof. Andy Tyrrell
Reconfigurable and Evolvable Architectures and their role in Designing Computational Systems,
Prof. Andy Tyrrell,
Department of Electronics, The University of York, UK
Time: 03:20pm - 03:50pm
Location: Gold Room

Abstract:

Biological inspiration in the design of computing machines finds its source in essentially three biological models: phylogenesis, the history of the evolution of the species, ontogenesis, ...

Bio:

Andy Tyrrell received a 1st class honours degree in 1982 and a PhD in 1985, both in Electrical and Electronic Engineering. He joined the Electronics Department at York University in April 1990, he was promoted to the Chair of Digital Electronics in 1998.

Prof. João M. P. Cardoso, "A New Approach to Control and Guide ..."

Prof. João M.P. Cardoso,
A New Approach to Control and Guide the Mapping of Computations to FPGAs,
Prof. João M.P. Cardoso, et al.,
University of Porto, Portugal
Time: 09:10am - 09:40am
Location: Gold Room

Abstract:

Field-Programmable Gate-Arrays (FPGAs) are becoming increasingly popular as computing platforms for high-performance embedded systems. Their flexibility and customization capabilities ...

Bio:

He is an Associate Professor with tenure at the Department of Informatics Engineering, Faculty of Engineering of the University of Porto. ...

Prof. Jörg Henkel, "iCore: A Run-time Adaptive Processor for ..."

Prof. Jörg Henkel
iCore: A Run-time Adaptive Processor for Embedded Multi-core Systems,
Prof. Jörg Henkel, Lars Bauer and Artjom Grudnitsky,
Karlsruhe Institute of Technology, Germany
Time: 09:50am - 10:20am
Location: Gold Room

Abstract:

We present the iCore (invasive core), an application specific instruction set processor (ASIP) with a run-time adaptive instruction set. Its adaptivity is controlled by the run-time system with respect to application properties that may vary during run-time. A reconfigurable fabric hosts the adaptive part of the instruction set whereas the rest of he instruction set is fixed. We show that the iCore is particularly beneficial in an embedded multi-core system where it performs applications-specific as well as system-specific tasks. The advantages are demonstrated by means of multi-media applications.

Bio:

Professor Jörg Henkel is currently with Karlsruhe Institute of Technology (KIT), Germany, where he is directing the Chair for Embedded Systems CES. Before, he was with NEC Laboratories in Princeton, NJ. His current research is focused on design and architectures for embedded systems with focus on low power and reliability. Prof. Henkel has organized various embedded systems and low power ACM/IEEE conferences/ symposia as General Chair and Program Chair and was a Guest Editor on these topics in various Journals like the IEEE Computer Magazine. He was Program Chair of CODES'01, RSP'02, ISLPED/06, SIPS'08 and CASES'09 and served as General Chair for CODES'02 and ISLPED 2009. He is/has been a steering committee member of major conferences in the embedded systems field like at ICCAD, Codes+ISSS and is also an editorial board member of various journals like the IEEE TVLSI, JOLPE etc. He has given full/half-day tutorials at leading conferences like DAC, ICCAD, DATE etc. Prof. Henkel received the 2008 DATE Best Paper Award and the 2009 IEEE/ACM William J. Mc Calla ICCAD Best Paper Award. He is the Chairman of the IEEE Computer Society, Germany Section, and the Editor-in-Chief of the ACM Transactions on Embedded Computing Systems (ACM TECS). He is an initiator and the spokes person of the German national program on 'Dependable Embedded Systems' (SPP 1500) funded by the German Science Foundation (DFG). He holds ten US patents.

ERSA’11 INVITED TALKS

Reconfigurable and Evolvable Hardware Architectures

Prof. Jeremy Buhler, "Systolic Arrays for Biosequence ..."

Prof. Jeremy Buhler
Design-Space Exploration of Systolic Arrays for Biosequence Algorithms,
Prof. Jeremy Buhler, Prof. Roger Chamberlain, and Dr. Arpith Jacob,
Washington University in St. Louis., USA
Time: 03:50 - 04:10pm
Location: Gold Room

Abstract:

The last decade has seen a revolution in technologies to sequence large amounts of DNA. Multiple order-of-magnitude improvements in speed and cost have made direct sequencing the biologist’s choice not only for determining the DNA sequence of a genome ...

Bio:

Jeremy Buhler is an associate professor in the Dept. of Computer Science and Engineering at Washington University in St. Louis. He leads the department’s High Performance Computational Biology Group. ...

Dr. Eric Stahlberg, "Heterogeneous Accelerated Bioinformatics..."

Dr. Eric Stahlberg
Heterogeneous Accelerated Bioinformatics — Perspectives for Impacting Cancer Research and Treatment,
Dr. Eric A. Stahlberg,
US National Cancer Institute, USA

Time: 04:10 - 04:30pm
Location: Gold Room

Abstract:

The presentation will provide insight into the areas where reconfigurable and fpga-based computing can contribute to accelerating bioinformatics ...

Bio:

Eric Stahlberg is the director for the bioinformatics core at the US National Cancer Institute. He was recently a visiting computational scientist employed by Wittenberg University where he directs the institution’s efforts in computational science while also serving as president of OpenFPGA Inc.

Prof. Jim Tørresen, "Run-time Reconfigurable Hardware ..."

Prof. Jim Tørresen
Can Run-time Reconfigurable Hardware be more Accessible?
Prof. Jim Tørresen,
University of Oslo, Norway
currently a visiting professor at Cornell University
Time: 01:40 - 02:00pm
Location: Gold Room

Abstract:

This talk will describe how we are applying FPGA technology for designing high performance run-time reconfigurable computing architectures. This is research undertaken through the project named Context Switching Reconfigurable Hardware for Communication Systems (COSRECOS), funded by the Research Council of Norway for 2009 — 2013.

Bio:

Jim Torresen received his M.Sc. and Dr.ing. (Ph.D) degrees in computer architecture and design from the Norwegian University of Science and Technology, University of Trondheim in 1991 and 1996, respectively.

Prof. Pao-Ann Hsiung, "A Self-Adaptive Hardware-Software System ..."

Prof. Pao-Ann Hsiung
SAHA: A Self-Adaptive Hardware-Software System Architecture for Ubiquitous Computing Applications,
Prof. Pao-Ann Hsiung and Chun-Hsian Huang,
National Chung Cheng University, Taiwan
Time: 02:00 - 02:20pm
Location: Gold Room

Abstract:

In ubiquitous computing environments, services and devices must be dynamically adapted to changing conditions and requirements. Thus, system adaptivity becomes a key requirement in providing better system performance. ...

Bio:

Pao-Ann Hsiung, Ph.D., received his B.S. in Mathematics and his Ph.D. in Electrical Engineering from the National Taiwan University, Taiwan, ROC, in 1991 and 1996, respectively. From 2001 to 2002, he was an assistant professor and from 2002 to 2007 he was an associate professor ...

Formal Methods and Engineering: Tools and Theory

Prof. David Andrews, "Develop Flows and Run Time Systems ..."

Prof. David Andrews
Design Flows and Run Time Systems for Heterogeneous Multiprocessor Systems on Programmable Chips (MPSOPCS)
Prof. David Andrews,
University of Arkansas, USA
Time: 01:20 - 01:40pm
Location: Gold Room

Abstract:

Emerging platform FPGAs will contain over 1 million LUTs, enough to support hundreds of soft programmable cores. This level of integration opens the potential for designers to switch approaches for performance increases from tedious accelerator point designs to more portable and efficient software based scalable parallel processing. ...

Bio:

David Andrews holds the Mullins Endowed Chair of Computer Engineering in the Computer Science and Computer Engineering (CSCE) Department at the University of Arkansas. ...

Security: Threats and Solutions

Prof. Ryan Kastner, "Bit-Tight Design: A Novel Design Methodology for..."

Prof. Ryan Kastner
Bit-Tight Design: A Novel Design Methodology for Reconfigurable Systems,
Prof. Ryan Kastner,
University of California San Diego, CA, USA
Time: 10:00 - 10:20am
Location: Gold Room

Abstract:

Trusted systems fundamentally rely on the ability to tightly control the flow of information both in-to and out-of the device. Due to their inherent programmability, reconfigurable systems are riddled with security holes (timing channels, undefined behaviors, storage channels, backdoors) which can be used as a foothold for attackers to strike. ...

Bio:

Ryan Kastner is an associate professor in the Department of Computer Science and Engineering at the University of California, San Diego. He received a PhD in Computer Science (2002) at UCLA, ...

Prof. Tim Güneysu, "High-Performance Cryptography"

Prof. Tim Güneysu
Establishing Dedicated Functions on Recent FPGA Devices for High-Performance Cryptography,
Prof. Tim Güneysu,
Applied Data Security and Cryptography, Ruhr University Bochum, Germany
Time: 09:20 - 09:40am
Location: Gold Room

Abstract:

This work presents a unique design approach for the implementation of standardized symmetric and asymmetric cryptosystems on modern FPGA devices. In contrast to many other FPGA implementations ...

Bio:

Tim Güneysu is an assistant professor leading the research group “Hardware Security” at Ruhr University of Bochum in Germany. Major research topics of his group are cryptographic and cryptanalytic implementations and systems, in particular involving reconfigurable devices.

Dr. Kimmo Järvinen, "High-Performance Implementation of ..., "

Dr. Kimmo Järvinen
High Performance Implementation of Elliptic Curve Cryptography with Reconfigurable Hardware,
Dr. Kimmo Järvinen,
Aalto University, Finland

Time: 09:40 - 10:00am
Location: Gold Room

Abstract:

This work presents a highly optimized FPGA-based implementation of elliptic curve cryptography. The work relies on the state-of-the-art algorithms and implementation techniques. Contrary to many other published elliptic curve processors, ...

Bio:

Dr. Järvinen is currently a postdoctoral researcher in the cryptography group of Department of Information and Computer Science at Aalto University in Espoo, Finland. He has been working in a European Union 7th Framework Programme project Computer Aided Cryptography Engineering ...


Visit ERSA Archive to see ERSA/WORLDCOMP Keynotes from previous years


ERSA’11 INVITED SESSIONS

Creating Science for Cyber-Security,
Chairs: Prof. Shiu-Kai Chin and Prof. William L. Harrison

Creating the Science & Engineering for Cyber-Security,

Prof. Shiu-Kai Chin
Chair:
Prof. Shiu-Kai Chin,
Syracuse University, USA
Senior Scientist, Serco-NA, Inc.

Bio:

Shiu-Kai Chin is a Professor in the Department of Electrical Engineering and Computer Science at Syracuse University, Syracuse, New York. His research applies mathematical logic to the engineering of trustworthy systems. ...

Prof. Shiu-Kai Chin
Chair:
Prof. William L. Harrison,
University of Missouri, USA

Bio:

William Harrison is an associate professor in the Department of Computer Science at the University of Missouri in Columbia, Missouri. His research applies structures and techniques ...

Abstract

Securing the Internet, electronic databases, protocols, financial services, telecommunications networks, power grids, military systems, and cyber-physical systems in general, is a widespread and growing concern. ...

Papers

Logic Design for Access,
Prof. Shiu-Kai Chin

Prof. Shiu-Kai Chin
Logic Design for Access Control, Security, Trust, and Assurance,
Prof. Shiu-Kai Chin,
Syracuse University, USA
Senior Scientist, Serco-NA, Inc.
Time: 11:20am - 11:50am
Location: Gold Room

Abstract:

Designers of hardware and software are frequently doing their work as part of larger systems where the confidentiality, integrity, and availability of information and other resources is a primary concern. Whether the system is a military one where assurance of mission critical capabilities is paramount, ...

Bio:

Shiu-Kai Chin is a Professor in the Department of Electrical Engineering and Computer Science at Syracuse University, Syracuse, New York. His research applies mathematical logic to the engineering of trustworthy systems. ...

The Nature of Cyber Security
Prof. Eugene Howard Spafford,

ERSA/WORLDCOMP KEYNOTE TALK

Prof. Eugene Howard Spafford
The Nature of Cyber Security,
Prof. Eugene Howard Spafford,
Purdue University, USA
Leading computer security expert
Time: 09:50 - 10:45am
Location: Lance Burton Theater

Abstract:

There is an on-going discussion about establishing a scientific basis for cyber security. Efforts to date have often been ad hoc and conducted without ...

Bio:

Eugene Howard Spafford is a Professor in the Purdue University. He is historically significant Internet figure, he is renowned for first analyzing the Morris Worm, one of the earliest computer worms, ...

Science of Mission Assurance,
Dr. Sarah Muccio

Dr. Sarah Muccio
Science of Mission Assurance,
Dr. Sarah Muccio,
Air Force Research Laboratory, USA
Time: 02:00 - 02:20pm
Location: Gold Room

Abstract:

We present a scientific framework for assuring mission essential functions in a contested cyber environment. s

Bio:

Dr. Sarah L. Muccio (BS Mathematics, Summa Cum Laude, Youngstown State University; MS, PhD Applied Mathematics, North Carolina State University) is a mathematician for the Cyber Science Branch ...

Grounding Trust,
Prof. Cynthia Irvine

Prof. Cynthia Irvine
Grounding Trust
Prof. Cynthia Irvine,
Naval Postgraduate School, USA
Time: 11:50am - 12:20pm
Location: Gold Room

Abstract:

The word “security” is often defined as “the freedom from danger” or “the freedom from doubt and fear.” Life is dangerous, ...

Bio:

Dr. Cynthia Irvine is the Director of the Center for Information Systems Security Studies and Research (CISR) and a Professor of Computer Science at the Naval Postgraduate School, ...

Information Flow and and Noninterference-style Security,
Dr. Gerard Allwein

Dr. Gerard Allwein
Information Flow and Noninterference-style Security
Dr. Gerard Allwein,
Naval Research Laboratory, USA

Time: 01:20 - 01:40pm
Location: Gold Room

Abstract:

It has long been held that information flow security models should be organized with respect to a theory of information, but typically they are not. ...

Bio:

Dr. Gerard Allwein is an algebraic logician with an undergrad degree in Computer Science from Purdue U. and PhD from Indiana U. He studies non-standard logics ...

"It Takes a Village" (to create a science): From crypto science to security science,
Dr. Steven Borbash

Dr. Steven Borbash
It Takes a “Village” (to create a science): From crypto science to security science
Dr. Steven Borbash ,
National Security Agency, USA
Time: 01:40 - 02:00pm
Location: Gold Room

Abstract:

Government funding for the solutions to security-related problems has increased significantly in the last decade, along with interest in these ...

Bio:

Steven Borbash is a Senior Researcher in Information Assurance at the National Security Agency. He has worked on problems of communications and computer security ...

The Confluence of Secure Hardware and Programming Languages,
Chair Prof. William L. Harrison

RC + LBS: The Confluence of Secure Hardware and Programming Languages,

Prof. William L. Harrison,
Chair:
Prof. William L. Harrison,
University of Missouri, USA

Bio:

William Harrison is an associate professor in the Department of Computer Science at the University of Missouri in Columbia, Missouri. His research applies structures and techniques ...

Abstract

Generating hardware from high-level languages is an active area of research within reconfigurable computing (RC). One motivation for this is to ...

Papers

3-D Extensions for Trustworthy Systems,
Dr. Ted Huffmire

Dr. Ted Huffmire
3-D Extensions for Trustworthy Systems
Ted Huffmire, Timothy Levin, Cynthia Irvine, Ryan Kastner, and Timothy Sherwood,
Naval Postgraduate School in Monterey, California, USA
Time: 08:10 - 08:30am
Location: Gold Room

Abstract:

Developing high assurance systems is costly. Trustworthy system development entails a high non-recurring engineering (NRE) cost together with a low volume of units over which to amortize that cost. ...

Bio:

Ted Huffmire is an Assistant Professor of Computer Science at the Naval Postgraduate School in Monterey, California. His research spans ...

Declarative FPGA Circuit Synthesis using Kansas Lava
Dr. Andrew Gill

Dr. Andrew  Gill
Declarative FPGA Circuit Synthesis using Kansas Lava,
Dr. Andrew Gill,
University of Kansas, USA

Time: 08:30 - 08:50am
Location: Gold Room

Abstract:

Designing and debugging hardware components is challenging, especially when performance requirements demands a complex orchestra of cooperating and highly synchronized computation engines.

Bio:

Andrew (Andy) Gill was born and educated in Scotland, and has spent his professional career in the United States. Andy received his Ph.D. from the University of Glasgow ...

Towards Semantics-directed System Design and Synthesis,
Prof. William L. Harrison

Prof. William L. Harrison
Towards Semantics-directed System Design and Synthesis,
Prof. William L. Harrison,
University of Missouri, USA
Time: 08:50 - 09:10am
Location: Gold Room

Abstract:

Synthesis of hardware from high level programming languages is a hot topic within reconfigurable computing. A recent trend in languages research, language-based security, applies ideas from programming language ...

Bio:

William Harrison is an associate professor in the Department of Computer Science at the University of Missouri in Columbia, Missouri. His research applies structures and techniques ...

Runtime Adaptive Embedded Systems and Architectures,
Chair Prof. Roman Lysecky

Runtime Adaptive Embedded Systems and Architectures,

Prof. Roman Lysecky
Chair:
Prof. Roman Lysecky,
University of Arizona, USA

Bio:

Roman Lysecky is an Assistant Professor of Electrical and Computer Engineering at the University of Arizona. He received his B.S., M.S., and Ph.D. in Computer Science from the University of California, ...

N/A bbb

Abstract

As complexity of embedded applications grows, predicting the dynamic execution behavior of embedded systems is increasingly challenging. Additionally, the environment in which a device is deployed and data being processed ...

Papers

iCore: A Run-time Adaptive Processor for Embedded Multi-core Systems,
Prof. Jörg Henkel

Prof. Jörg Henkel
iCore: A Run-time Adaptive Processor for Embedded Multi-core Systems,
Prof. Jörg Henkel, Lars Bauer and Artjom Grudnitsky,
Karlsruhe Institute of Technology, Germany
Time: 09:50am - 10:20am
Location: Gold Room

Abstract:

We present the iCore (invasive core), an application specific instruction set processor (ASIP) with a run-time adaptive instruction set. ...

Bio:

Professor Jörg Henkel is currently with Karlsruhe Institute of Technology (KIT), Germany, where he is directing the Chair for Embedded Systems CES. Before, he was with NEC Laboratories in Princeton, ...

Advanced Profiling of Applications for Heterogeneous Multi Core Platforms
Prof. Koen Bertels

Prof. Koen Bertels
Advanced Profiling of Applications for Heterogeneous Multi Core Platforms,
Prof. Koen Bertels, Arash Ostadzadeh, Roel Meeuws
Delft University, The Netherlands

Time: 10:40 - 11:00am
Location: Gold Room

Abstract:

The increased complexity of programming on multi-processors platforms requires more insight into program behavior for which programmers need increasingly sophisticated methods for profiling, ...

Bio:

Koen Bertels is an associate professor in the Computer Engineering group where he heads the Delft Workbench Project that aims to develop an entire tool chain offering semi-automated ...

How Parameterizable Run-time FPGA-Reconfiguration Can Benefit Adaptive Embedded Systems,
Dr. Dirk Stroobandt,

Dirk Stroobandt
How Parameterizable Run-time FPGA- Reconfiguration can Benefit Adaptive Embedded Systems,
Dirk Stroobandt, Karel Bruneel
Ghent University, Belgium

Time: 11:00 - 11:20am
Location: Gold Room

Abstract:

In this presentation, we assume that runtime adaptive embedded systems have proven benefits over static implementations and we ask ourselves how such an adaptive system could be implemented. It is clear that the system adaptation ...

Bio:

Dirk Stroobandt graduated in 1994 and obtained the Ph.D. degree in 1998 in electrotechnical engineering from Ghent University, Belgium. Until 2002 he was post-doctoral fellow with the Fund for Scientific Research - Flanders (Belgium) (F.W.O.) and and 2002 he was appointed ...

How to Effectively Program Reconfigurable Multi-Core Embedded Systems?,
Chair Dr. Pedro C. Diniz

Dr. Pedro C. Diniz
How to Effectively Program Reconfigurable Multi-Core Embedded Systems?,
Chair:
Dr. Pedro C. Diniz,
Univ. of California at Santa Barbara, USA

Bio:

Dr. Diniz received his M.S. in Electrical and Computer Engineering from the Technical University in Lisbon, Portugal and his Ph.D. from the University of California, ...

Abstract

The ability to continually increase the number of available transistors on a die has lead to the emergence of the many-core and multi-core computing architectures promising the potential for order of magnitude performance improvements over single core solution through sheer concurrency. ...

Papers

Heterogeneous Multicore Computing: Challenges and Opportunities. Experiences from the hArtes Project,
Prof. Koen Bertels

Prof. Koen Bertels
Heterogeneous Multicore Computing: Challenges and Opportunities. Experiences from the hArtes Project,
Prof. Koen Bertels and Vlad-Mihai Sima and Georgi Kuzmanov,
Technical University of Delft (TUD), Germany
Time: 08:10 - 08:30am
Location: Gold Room

Abstract:

This paper discusses the different problems that were encountered during the hArtes project and how those challenges where met....

Bio:

Koen Bertels is an associate professor in the Computer Engineering group where he heads the Delft Workbench Project that aims to develop an entire tool chain offering semi-automated ...

Runtime Resource Runtime Resource Management Techniques for Many-core Architectures: The 2PARMA Approach,
Dr. Alexandros Bartzas,

Dr. Alexandros Bartzas
Runtime Resource Runtime Resource Management Techniques for Many-core Architectures: The 2PARMA Approach,
Dr. Alexandros Bartzas, et al.,
Institute of Communications and Computer Systems, Athens, Greece,

Time: 10:40 - 11:00am
Location: Gold Room

Abstract:

The current trend in computing architectures is to replace complex superscalar architectures with meshes of small homogeneous processing units connected ...

Bio:

N/A

A New Approach to Control and Guide the Mapping of Computations to FPGAs,
Prof. João M. P. Cardoso, et al.,

Prof. João M.P. Cardoso,
A New Approach to Control and Guide the Mapping of Computations to FPGAs,
Prof. João M.P. Cardoso, et al.,
University of Porto, Portugal
Time: 09:10am - 09:40am
Location: Gold Room

Abstract:

Field-Programmable Gate-Arrays (FPGAs) are becoming increasingly popular as computing platforms for high-performance embedded systems. Their flexibility and customization capabilities ...

Bio:

He is an Associate Professor with tenure at the Department of Informatics Engineering, Faculty of Engineering of the University of Porto. ...

ERSA’11 PANELS

ERSA’11 TUTORIALS

A Run-Time Evolvable Hardware,
Prof. Jim Tørresen

Prof. Jim Tørresen
A Run-Time Evolvable Hardware,
Prof. Jim Tørresen,
University of Oslo, Norway
currently a visiting professor at Cornell University

Abstract:

Traditional hardware design aims at creating circuits which, once fabricated, remain static during run-time. This changed with the introduction of reconfigurable technology and devices (typically FPGAs) which opened up the possibility of dynamic hardware. However, the potential of dynamic hardware for the construction of self-adaptive, self-optimizing and self-healing systems can only be realized if automatic design schemes are available.

Bio:

Jim Torresen received his M.Sc. and Dr.ing. (Ph.D) degrees in computer architecture and design from the Norwegian University of Science and Technology, University of Trondheim in 1991 and 1996, respectively.

N/A

Recipient of ERSA/WORLDCOMP 2010 Award

OUTSTANDING ACHIEVEMENT AWARD

Jon Huppenthal Jon Huppenthal

President and Chief Executive Officer, SRC Computers, LLC
Co-Founder (with Late Seymour Cray)


In Recognition of his Leadership, Outstanding Research &
Technical Contributions to the field of Heterogeneous Systems


Visit ERSA Archive to see ERSA/WORLDCOMP awards from previous years


Dr Toomas P Plaks

Conference Chair
Dr Toomas P Plaks

London
Contact the Chair

Important Dates

Proposals for sessions:
  • Specialised Research Sessions
    Jan. 15, 2011
  • Research Project Sessions
    March 1, 2011
Regular Papers:
  • Submission is open until
    April 15, 2011
  • Notification
    May 4, 2011
  • Final Papers
    May 18, 2011

E-mail Directory

  • General Inquiries:
    inf@ersaconf.org
  • Paper Submission:
    sub@ersaconf.org
    No inquiries
  • CFP are sent:
    mail@ersaconf.org
    Don't reply

WEB Directory

  • ERSA HOMEPAGE:
    http://ersaconf.org
  • ERSA News:
    http://ersaconf.org/news
  • ERSA Conferences:
    http://ersaconf.org/ersa##
    where ## is 07, 08, 09, 10, 11
  • ERSA Mobile:
    http://ersaconf.org/ersa##_mobi
  • ERSA Archive:
    http://ersaconf.org/arhcive