Embedded Processor Selection Using FPGA-based Profiling Fadi Obeidat* and Robert H. Klenke**
* Intel Corporation, Austin, TX, USA
** Virginia Commonwealth University, Virginia, USA
In embedded systems, modeling the performance of off-the-shelf processors is very important to
enable the designer to estimate the capability of each candidate processor against the target
application. Considering the large number of available embedded processors, the need has increased
for building an infrastructure by which it is possible to estimate the performance of a given
application on a certain processor with a minimum of time and resources. This paper presents
the use a Xilinx MicroBlaze softcore processor ...
How we drive is set for major changes as the rise of advanced driver assistance systems,
connected cars, and big data analytics make mobility quicker, safer, and greener. However,
until recently, this next evolutionary stage of technology has largely inhabited the murky
realms of slideware, rather than actual reality.
Big data analytics draws out the useful information, which is turned into driver updates
through connected equipment ranging from smartphones to navigation systems.
U.S. Navy Fires "XFC" Drone from Underwater Submarine
Here's how it works: using the the Los Angeles class USS Providence (SSN 719) and
the Naval Undersea Warfare Center-Newport Division (NUWC-NPT), NRL was able to fire
XFC UAS from the submarine's torpedo tube using a Sea Robin launch vehicle system.
This particular launch system is designed to fit within an empty Tomahawk launch canister (TLC).
After many years of hype, multicore and multiple-CPU embedded systems are now becoming mainstream.
There are numerous articles about multicore design that address different hardware architectures
(homogeneous and heterogeneous multicore) and software architectures (AMP: asymmetrical multi-processing
and SMP: symmetrical multi-processing). In this article the development of an AMP system is outlined,
highlighting various challenges that were addressed. What is unusual is that the design was completed in 1981!
Altera offers the 40 Gbps Ethernet (40GbE) and 100 Gbps Ethernet (100GbE) MegaCore ®
function intellectual property (IP) cores for building systems with very high throughput-rate
standard Ethernet connections. These IEEE 802.3ba-2010 40 Gbps and 100 Gbps Ethernet standard
compliant media access control (MAC) and PHY (PCS+PMA) IP cores enable an Altera ® device to
interface to another device or to an optical transceiver module and, in turn, to 40GbE and 100GbE networks.
OpenSPL consortium unveils standard for spatial computing
OpenSPL is an open standard for a novel Spatial Programming Language. It is based on
the core concept that a program executes in space, rather than in time sequence.
All operations are assumed to be parallel unless specified to be sequential.
This is similar to a factory floor where all operations execute in parallel,
but each operation executes a different part of the overall process. Temporal
Programming is a recipe for the execution of actions, whereas Spatial Programming
builds a factory to execute the recipe.
Global Cyber Espionage Concerns Reveal Growing Cyber Armies
There is growing political tension between nations competing in a cyber-arms race,
while cooperating nations are unable to agree to international cyber guidelines to address cyber-attacks.
Targeted espionage and coordinated cyber-attacks continues to increase from
2012 through 2014, according to security company Symantec, in a report published
earlier in the year. Targeted attacks increased 42 percent in 2012 alone, as cyber
criminals look for exploits and security back doors before patches are developed.
The Application Developer Journal is a companion to the international
conference on Engineering of
Reconfigurable Systems and Algorithms (ERSA) , and will turn the
ERSA conference into
year-around event. Las Vegas is just the place where researchers
and entrepreneurs can meet and talk face-to-face.
Rapid publication of short papers and advertising in Developer Newsletter is
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in the next issue of the newsletter.
Publishing technical papers may take up to two weeks.
Publishing technical papers and advertisements during the introduction period of this journal is free.
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Company or Event Banner (with link to website), it can be an animated GIF, but animation not required
Company Logo or Banner (with link to website) plus Company or Event Info (half page + one image)
Logos are usually displayed on the left bar of the website and journal. Banners are usually horizontal
graphical blocks (in some cases we accept vertical banners)
and displayed at the bottom or middle area of the webpage and journal.
Advertisements are displayed on a separate
webpage with its own URL and are supported by LinkedIn button.
See for example
Advertising are sold for one month, three months and for whole year.
Only commercial advertising will be charged. Advertising of upcoming events,
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Currently, you have to email you technical paper (short or full-size) to
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Publishing, on a separate webpage with LinkedIn button
All contributions to the ADN journal in a form of text (i.e. not merely Logos),
including advertisings and short papers,
are displayed on a separate
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the contribution to LinkedIn groups and to forward to other individuals.
In this way, authors and their contributions will be benefited with higher visibility.
The Journal for
Developers of Heterogeneous Computing Systems
The Application Developer News - ADN is a Journal
for industrial and academic researchers, entrepreneurs, and developers. It offers
peer-reviewed, rapid-decision publishing,
focusing on commercial application development for heterogeneous, reconfigurable,
embedded computing systems. The journal will be published monthly.
Editorial Message and
more about the Scope.
Developer Newsletter is a weekly update of news for Developers of Heterogeneous Computing Systems.
It is published on every Wednesday, distributed freely by email and is available on
Application Developer News website .
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If you are interested to be an editor, please contact with the EiC,
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