has been held as an important part of WORLDCOMP:
In this paper, we present an overview of new watermarking and identification techniques for FPGA IP cores. Unlike most existing watermarking techniques, the focus of our techniques lies on ease of verification, even if the protected cores are embedded into a product. Moreover, we have concentrated on higher abstraction levels for embedding the watermark, particularly at the logic level, where IP cores are distributed as netlist cores. With the presented watermarking methods, it is possible to watermark IP cores at the logic level and identify them with a high likelihood and in a reproducible way in a purchased product from a company that is suspected to have committed IP fraud. The investigated techniques establish the authorship by verification of either an FPGA bitfile or the power consumption of a given FPGA.
Jürgen Teich received his masters degree (Dipl.-Ing.) in 1989 from the University of Kaiserslautern (with honours). From 1989 to 1993, he was PhD student at the University of Saarland, Saarbruecken, Germany from where he received his PhD degree (summa cum laude). His PhD thesis entitled `A Compiler for Application-Specific Processor Arrays' summarizes his work on extending techniques for mapping computation intensive algorithms onto dedicated VLSI processor arrays. In 1994, Dr. Teich joined the DSP design group of Prof. E. A. Lee and D.G. Messerschmitt in the Department of Electrical Engineering and Computer Sciences (EECS) at UC Berkeley where he was working in the Ptolemy project (PostDoc).
From 1995 to 1998, he held a position at Institute of Computer Engineering and Communications Networks Laboratory (TIK) at ETH Zurich, Switzerland, finishing his Habilitation entitled `Synthesis and Optimization of Digital Hardware/ Software Systems' in 1996.
From 1998 to 2002, he was full professor (C4) in the Electrical Engineering and Information Technology department of the University of Paderborn, holding a chair in Computer Engineering.
Since 2003, he is appointed full professor (C4) in the Department of Computer Science of the Friedrich-Alexander University Erlangen-Nuremberg holding a chair in Hardware/Software Co-Design. Dr. Teich has been a member of multiple program committees of well-known conferences and workshops. He is a Senior Member of the IEEE and author of a textbook on Co-Design edited by Springer in 2007. His research interests are massive parallelism, embedded systems, Co-Design, and computer architecture.
Since 2004, Prof. Teich is also an elected reviewer for the German Research Foundation (DFG) for the area of Computer Architecture and Embedded Systems. Prof. Teich is involved in many interdisciplinary national basic research projects as well as industrial projects. He is supervising more than 30 PhD students currenty. Since 2010, he is also the coordinator of the Transregional Research Center 89 on Invasive Computing funded by the DFG.
Daniel Ziener took his university entrance qualification in 1998. He received his diploma degree (Dipl.-Ing. (FH)) in Electrical Engineering from University of Applied Science Aschaffenburg, Germany, in August 2002. Beside his studies, he gained industrial research experience during an internship at the IBM Germany Development Labs in Böblingen. From 2003 to 2009 he worked for the Fraunhofer Institute of Integrated Circuits (IIS) in Erlangen, Germany as a research staff in the electronic imaging department. Furthermore, in 2003 he joined the Chair of Hardware-Software-Co-Design at the University of Erlangen-Nuremberg, Germany, headed by Prof. Jürgen Teich as PhD student. In 2010 he received his PhD degree (Dr.-Ing.). The title of his PhD thesis is: “Techniques for Increasing Security and Reliability of IP Cores Embedded in FPGA and ASIC Designs”. Since 2010 he leads the Reconfigurable Computing Group at the Chair of Hardware-Software-Co-Design at the University of Erlangen-Nuremberg.
His main research interests are IP core watermarking, efficient usage of FPGA structures, design of signal processing FPGA cores, and reliable and fault tolerant embedded systems. Daniel Ziener has been a reviewer for several international conferences, for the IET Journal on Computers & Digital Techniques, the IEEE Transactions on Very Large Scale Integration Systems, and the Elsevier Journal for Microprocessors and Microsystems.