In this paper we present an analysis of how the growth of data sets has funded the development of hardware accelerated data filters. The hardware of choice in 2012/2013 appears to be field programmable gate arrays due to their inherent flexibility in I/O configuration and the ability to parallelize algorithms intended originally for CPU, to refactor them for optimal functionality in FPGA. The article assumes expertise in data but only moderate familiarity with tools and techniques for handling field programmable gate arrays. The authors strive to a realistic assessment of the new methodologies with sensitivity to the (occasionally significant) differences with the compilation path involved in contrast to CPU or GPU compilation.
Brian Durwood is co-founder and CEO of Impulse Accelerated Technologies Inc., makers of the Impulse C to FPGA optimizing compiler. His history in programmable logic dates back to Data I/O in the 80s, when it launched an early HDL called ABEL. His current focus is on tools, IP, and design services that help software developers be more productive accelerating code in FPGAs. Brian's blog on All Programmable Planet addresses issues common to hardware/software co-design. He was previously a VP at the Tektronix high-frequency multichip module facility. He is a graduate of Brown and Wharton and lives in the San Francisco Bay area.
Edward Trexel runs Engineering and Design Services at Impulse. He has helped over 100 design teams accelerate microprocessor code on FPGAs from Altera and Xilinx. Ed is an electrical engineering graduate of the University of Colorado.
Alan Coppola has spent the last few years working on FPGA acceleration of large scale R-language Bayesian Markov Chain Monte Carlo simulation applications, and on computer vision applications involving in-video search for image-objects and augmented reality mobile applications.