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Developer Newsletter

Wednesday, May 27, 2015

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point Call
for Contributions

Call for technical communities to submit:

Bullet Regular Technical and Research Papers

Bullet Proposals for Special Issues

Visit Call for Papers and Special Issues

Hot Topics:

Bullet Heterogeneous Systems Architecture

Bullet High Level Design Tools

Bullet Embedded Systems

Bullet Defence, Military and Space Applications

Bullet Mobile Computing Systems

Bullet Cloud Computing and Networking

Bullet Internet of Things and Wearables

Bullet Internet Security, Cryptography

Bullet Application in Automotive Industry, Autotainment

Bullet Bio-sciences, Bio-informatics, Medical Systems

Bullet HPC in Finance and Banking, Big Data

Bullet And More

Special Offer

Bullet 30% Discount
Full Size Technical Papers

Various discounts for non-profit organisations

Bullet Short Technical Papers

Bullet Advertising

Contact the EiC, Toomas P Plaks

ERSA-ADN Partners & Sponsors

Parallella Community

Supercomputing for
Everyone

Bullet Please forward the Newsletter to your colleagues and interested parties

Application Developer News - ADN

The Journal for
Developers of Heterogeneous Computing Systems

When Intel Buys Altera: Will FPGAs Take Over the Data Center?


Comments by Kevin Morris, Kevin Cameron, Reiner Hartenstein, Steve Casselman...

LinkedIn Discussion

Steve Casselman: FPGAs will completely dominate the data center. In the big data area you don’t really need cache you need FIFOs and streams. There is no “data reuse” when you are indexing an unstructured data set.

News from World

No particular order

Bullet FPGAs Ride HP’s Moonshot

SRC hopes to fuel Moonshot sales with its $20,000 4U card (pictured below) that hosts two Altera Stratix IV 530 FPGAs. The company claims the 45W board delivers 100 times the performance of an x86 server while using one percent of its power. The board also hosts a four-core Intel Atom chip for housekeeping duties and supports multiple Gbit Ethernet links to the Moonshot backplane.

The company was co-founded in 1996 by supercomputer guru Seymour Cray. Its secret sauce is its Carte compiler that automatically turns users’ C-level code into FPGA-readable firmware, eliminating the need for often complex Verilog-level FPGA programming tools. The FPGA also lets users quickly change code as workloads shift.

Bullet A Deeper Look at POWER8 CAPI and Data Engine for NoSQL

NoSQL and CAPI create a new tier of memory by attaching up to 40 TB of auxiliary flash memory to the processor without the latency issues of traditional I/O storage.

This article explains CAPI (Coherent Accelerator Processor Interface) technology and describes how it’s being used in the Data Engine for NoSQL, the first exploiter of the CAPI platform.

IT organizations must provide increased system performance as their workloads grow with demands for big data analysis, social media applications, technical computing, continuous customer connectivity and business-specific applications. Increases in processor performance can no longer satisfy the workload demands, so solutions must also come from system-level advances such as hybrid computing, processing engine customization and open platform development that enables cross-company innovation.

Many solutions will keep improving price-performance through specific function accelerators. These accelerators are delivered by GPU- and field-programmable gate array (FPGA)-based solutions. We already see these solutions today with I/O-attached acceleration engines, such as an NVIDIA GPU placed on a PCIe card.

  • Can TI Obsolete FPGAs?

Software Defined Hardware

No particular order

Bullet A Deeper Look at POWER8 CAPI and Data Engine for NoSQL

NoSQL and CAPI create a new tier of memory by attaching up to 40 TB of auxiliary flash memory to the processor without the latency issues of traditional I/O storage.

This article explains CAPI (Coherent Accelerator Processor Interface) technology and describes how it’s being used in the Data Engine for NoSQL, the first exploiter of the CAPI platform.

IT organizations must provide increased system performance as their workloads grow with demands for big data analysis, social media applications, technical computing, continuous customer connectivity and business-specific applications. Increases in processor performance can no longer satisfy the workload demands, so solutions must also come from system-level advances such as hybrid computing, processing engine customization and open platform development that enables cross-company innovation.

Many solutions will keep improving price-performance through specific function accelerators. These accelerators are delivered by GPU- and field-programmable gate array (FPGA)-based solutions. We already see these solutions today with I/O-attached acceleration engines, such as an NVIDIA GPU placed on a PCIe card.

Bullet Can TI Obsolete FPGAs?

Texas Instruments (TI) has thrown down the gauntlet to the field programmable gate array (FPGA) community — mostly Altera and Xilinx — by starting a family of special-purpose processors that combine multicore ARM processors with multicore digital signal processors (DSPs) and multiple programmable hardware accelerators. Can they pull it off? An FPGA is like a blank-slate that can solve any high-speed computational problem, but at a high-price, difficult programming and a waste of resources (not every gate is used in the vast majority of FPGA designs).

On the other hand, TI will have to create an expanding family of special-purpose chips to address all the niche markets that FPGAs address. Can it be done? We asked TI, Altera and a bevy of analysts what their opinions were and summarized them below.

  • Xilinx Loses Its Tail.
    The Next Evolutionary Step After FPGAs?
  • FPGAs Ride HP’s Moonshot

Cybersecurity Threats

No particular order

Bullet 2014 Data Breach Investigations Report

Gain fresh insight into cyber espionage and denial-of-service attacks in the 2014 Data Breach Investigations Report (DBIR).

For DBIR veterans, a cursory look at the table of contents will reveal some significant changes to the report structure you’ve gotten used to in years past. Rather than our signature approach organized around actors, actions, assets, timelines, etc., we’ve created sections around common incident patterns derived directly from the data itself (more on that later). Within each of those patterns, we cover the actors who cause them, the actions they use, assets they target, timelines in which all this took place, and give specific recommendations to thwart them. The drive for change is three-fold: first, we realized that the vast majority of incidents could be placed into one of nine patterns; second, we can (and did) draw a correlation between these incident patterns and industries; and third, we wanted to challenge ourselves to look at the data with a fresh perspective. The ultimate goal is to provide actionable information presented in a way that enables you to hash out the findings and recommendations most relevant to your organization.

  • Countdown to Compromise: The Timeline of a Spear-Phishing Attack on Your Organization
  • Cisco 2015 Annual Security Report
  • CYBERCRIME 2015. An Inside Look at the Changing Threat Landscape
  • GameOver Zeus Botnet Disrupted
  • 2015 Data Breach Investigations Report

Most Visited ERSA-ADN Papers

From Streaming Models to FPGA Implementations
Hugo Andrade, Jeff Correll, Amal Ekbal, Arkadeb Ghosal, et al.
National Instruments Corporation, USA
forward
How Parameterizable Run-time FPGA- Reconfiguration can Benefit Adaptive Embedded Systems
Dirk Stroobandt, Karel Bruneel
Ghent University, Belgium
forward
Ensuring Design Integrity through Analysis of FPGA Bitstreams and IP Cores
Jonathan P. Graf
Luna Innovations Inc., USA
forward
Elliptic curve cryptography on FPGAs: How fast can we go with a single chip?
Dr. Kimmo Järvinen
Aalto University, Finland
forward
Software-Based Reconfigurable Computing Platform (AppSTARTM) for Multi-Mission Payloads in Spaceborne and Near-Space Vehicles
Dr. Edward R. Beadle and Dr. Tim Dyson
Harris Corporation, USA
forward
Towards OpenCL Compilation into High-Performance Hardware for FPGAs
Prof. Stephen Brown
University of Toronto & Altera, Canada
forward
How Engineering Mathematics can Improve Software
Prof. David Lorge Parnas
Middle Road Software, Inc, Canada
forward
Flow-Based Programming
J. Paul Morrison
J.P. Morrison Enterprises Ltd., Unionville, Ontario, Canada
forward
Reconfigurable and Evolvable Architectures and their role in Designing Computational Systems
Prof. Andy Tyrrell
The University of York, UK
forward

Back to Contents

ADN Technical Papers

Embedded Processor Selection Using FPGA-based Profiling
Fadi Obeidat* and Robert H. Klenke**
* Intel Corporation, Austin, TX, USA
** ECE Department, Virginia Commonwealth University, Richmond, Virginia, USA
forward
Flow-Based Programming
J. Paul Morrison
J.P. Morrison Enterprises Ltd., Unionville, Ontario, Canada
forward
High Performance Computing for Scientific and Technical Applications. A brief history and reality today
Lindsay M Black
MIET, MIEEE
forward
High Level Design of Hardware-based, Low-Latency Filters for “Big Data”
Brian Durwood*, Edward Trexel* and Alan Coppola**
*Impulse Accelerated Technologies Inc, USA
**OptNgn Software, USA
forward

Back to Contents

point Technical Info for ADN Contributors

Bullet Types of Advertisings

There are three main options for advertising.

  • Company or Event Logo plus link to Company or Event web-site
  • Company or Event Banner (with link to website), it can be an animated GIF, but animation not required
  • Company Logo or Banner (with link to website) plus Company or Event Info (half page + one image)

Logos are usually displayed on the left bar of the website and journal. Banners are usually horizontal graphical blocks (in some cases we accept vertical banners) and displayed at the bottom or middle area of the webpage and journal.

Advertisements are displayed on a separate webpage with its own URL and are supported by LinkedIn button. See for example Velocytech webpage with ERSA/ADN.

Advertising are sold for one month, three months and for whole year.

Only commercial advertising will be charged. Advertising of upcoming events, seminars, conferences, webinars, etc are free.

Read More forward

Bullet Submission

Email submission

Currently, you have to email your technical paper (short or full-size) to sub@ersaconf.org in PDF format. In case of advertisements, you have to send the Logo or Banner as a separate file, text of advertisement as a PDF file.

On the subject line, you have to specify that this is a submission for Application Developer Journal, and the name of corresponding author:

SUBJECT LINE:
Application Developer Journal, [first name, family name]

In the body, please include the title of the paper, names of authors and corresponding author.

Cover Letter

Each submission must include a cover letter as a separate .txt file and containing the following information:

  • the title of paper
  • authors with their affiliations
  • contacting author's name, full postal address, e-mail address, telephone number
  • type of paper: full paper, short paper
  • 3 to 6 topical keywords that would best represent the content of the paper

For further details, contact the EiC, Toomas P Plaks.

Read More forward

Bullet Publishing on Web site

Publishing on a separate webpage with LinkedIn button

All contributions to the ADN journal in a form of text (i.e. not merely Logos), including advertisings and short papers, are displayed on a separate webpage with its own URL and are supported by LinkedIn button. This offers authors and visitors the possibility to post the contribution to LinkedIn groups and to forward to other individuals. In this way, authors and their contributions will be benefited with higher visibility.

Application Developer News - ADN

The Journal for
Developers of Heterogeneous Computing Systems

The Application Developer News - ADN is a Journal for industrial and academic researchers, entrepreneurs, and developers. It offers peer-reviewed, rapid-decision publishing, focusing on commercial application development for heterogeneous, reconfigurable, embedded computing systems. The journal will be published monthly. Read the Editorial Message and more about the Scope.

Developer Newsletter is a weekly update of news for Developers of Heterogeneous Computing Systems. It is published on every Wednesday, distributed freely by email and is available on Application Developer News website .

Editorial Board

ADN will draw on technical communities for peer reviewers to ensure the best possible papers are being published.

If you are interested to be an editor, please contact with the EiC, Toomas P Plaks.

ERSA & ADN Chair
Dr. Toomas P Plaks, London, UK

Contact the EiC,
Toomas P Plaks

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