Prof. Ryan Kastner
Bit-Tight Design: A Novel Design Methodology for Reconfigurable Systems,
Prof. Ryan Kastner,
University of California San Diego, CA, USA
Time: 10:00 - 10:20am
Location: Gold Room


Trusted systems fundamentally rely on the ability to tightly control the flow of information both in-to and out-of the device. Due to their inherent programmability, reconfigurable systems are riddled with security holes (timing channels, undefined behaviors, storage channels, backdoors) which can be used as a foothold for attackers to strike. System designers are constantly forced to respond to these attacks, often only after significant damage has been inflicted. We propose to use the reconfigurable nature of the system to our advantage by creating a new hardware foundation for secure computing which will carefully and precisely manage all flows of information, making them explicit and verifiable from the hardware logic gates all the way up the system stack. This can be used to ensure private keys are never leaked (for secrecy), and that untrusted information will not used in the making of critical decisions (for safety and fault tolerance) nor in determining the schedule (real-time).


Ryan Kastner is an associate professor in the Department of Computer Science and Engineering at the University of California, San Diego. He received a PhD in Computer Science (2002) at UCLA, a masters degree in engineering (2000) and bachelor degrees (BS) in both Electrical Engineering and Computer Engineering (1999), all from Northwestern University. He spent the first five years after his PhD as a professor in the Department of Electrical and Computer Engineering at the University of California, Santa Barbara.

Professor Kastner's current research interests reside in the realm of embedded system design, in particular, the use of reconfigurable computing devices for digital signal processing as well as hardware security. He has published over 100 technical articles, and has authored three books, "Synthesis Techniques and Optimizations for Reconfigurable Systems", "Arithmetic Optimizations for Polynomial Expressions and Linear Systems" and "Handbook on FPGA Design Security". He has served as member of numerous conference technical committees spanning topics like reconfigurable computing (ISFPGA, FPL, FPT, ERSA, RAW, ARC), electronic design automation (DAC, ICCAD, DATE, ICCD, GLSVLSI), wireless communication (GLOBECOM, SUTC), hardware security (HOST) and underwater networking (WUWNet). He serves on the editorial board for the IEEE Embedded Systems Letters.