has been held as an important part of WORLDCOMP:
In this paper, we introduce a novel, broad definition of field programmable gate array (FPGA) design integrity and explore its value in the domains of Trust, high-reliability design, and design anti-obsolescence for FPGA-based systems. We claim that an FPGA design with integrity must continuously provide the FPGA user with the function described by the designer and no other function. A common starting point for approaching design integrity in each of the explored domains is the FPGA bitstream. Luna’s unique software that evaluates the previously inaccessible designs inside of these bitstreams and third-party intellectual property (IP) provides a firm foundation for analysis of FPGA design integrity.
Jonathan Graf directs the research, development, and deployment of Luna’s Secure Computing and Communications (SCC) technologies. He concentrates on FPGA design integrity solutions that ensure design trust, enable high-reliability verification, migrate designs from obsolete FPGAs to modern parts, and provide FPGA design and security analysis. At Luna, he has served in the role of Principal Investigator and Project Manager for Luna’s prime contracts on two DARPA BAA programs related to FPGA Trust: DARPA Trust and DARPA IRIS. He has also served as Principal Investigator for 18 DoD SBIR projects. He is responsible for fostering Luna’s SCC technologies from inception to market in both defense and commercial arenas. Prior to Luna, Jonathan worked for Intel, Sprint, and three small startups. In addition to ERSA, his publications and invited talks in the past year have included the DoD Anti-Tamper Conference, the Microelectronic Circuit Analysis and Reverse Engineering Conference, the Government Microcircuit Applications and Critical Technology Conference, the Xilinx Safety and Reliability Consortium, the Army Research Office Workshop on Hardware Assurance, and the corporate Anti-Tamper conferences for both Xilinx and Lockheed Martin.