Dr Toomas P Plaks

Conference Chair
Dr Toomas P Plaks

London
Contact the Chair

LinkedIn connection requests welcome

ERSA Partners

ERSA Media Sponsor

ERSA’12 PROGRAMME

ERSA KEYNOTE TALK

Jonathan P. Graf
Ensuring Design Integrity through Analysis of FPGA Bitstreams and IP Cores,
Jonathan P. Graf
Luna Innovations Inc., USA
Time: 11:20 - 12:20am:
Location: Gold Room

Abstract:

In this paper, we introduce a novel, broad definition of field programmable gate array (FPGA) design integrity and explore its value in the domains of Trust, high-reliability design, and design anti-obsolescence for FPGA-based systems. We claim that an FPGA design with integrity must continuously provide the FPGA user with the function described by the designer and no other function. A common starting point for approaching design integrity in each of the explored domains is the FPGA bitstream. Luna’s unique software that evaluates the previously inaccessible designs inside of these bitstreams and third-party intellectual property (IP) provides a firm foundation for analysis of FPGA design integrity.

Bio:

Jonathan Graf directs the research, development, and deployment of Luna’s Secure Computing and Communications (SCC) technologies. He concentrates on FPGA design integrity solutions that ensure design trust, enable high-reliability verification, migrate designs from obsolete FPGAs to modern parts, and provide FPGA design and security analysis. At Luna, he has served in the role of Principal Investigator and Project Manager for Luna’s prime contracts on two DARPA BAA programs related to FPGA Trust: DARPA Trust and DARPA IRIS. He has also served as Principal Investigator for 18 DoD SBIR projects. He is responsible for fostering Luna’s SCC technologies from inception to market in both defense and commercial arenas. Prior to Luna, Jonathan worked for Intel, Sprint, and three small startups. In addition to ERSA, his publications and invited talks in the past year have included the DoD Anti-Tamper Conference, the Microelectronic Circuit Analysis and Reverse Engineering Conference, the Government Microcircuit Applications and Critical Technology Conference, the Xilinx Safety and Reliability Consortium, the Army Research Office Workshop on Hardware Assurance, and the corporate Anti-Tamper conferences for both Xilinx and Lockheed Martin.

fig_09

ERSA KEYNOTES

Prof. Stephen Brown "Towards OpenCL Compilation into High-Performance Hardware for FPGAs"

Prof. Stephen Brown
Towards OpenCL Compilation into High-Performance Hardware for FPGAs,
Prof. Stephen Brown,
University of Toronto & Altera, Canada
Time: 01:20 - 02:20pm
Location: Gold Room

Dr. Edward R. Beadle, "Software-Based Reconfigurable Computing Platform..."

Dr. Edward R. Beadle
Software-Based Reconfigurable Computing Platform (AppSTARTM) for Multi-Mission Payloads in Spaceborne and Near-Space Vehicles ,
Dr. Edward R. Beadle and Dr. Tim Dyson,
Harris Corporation, USA
Time: 03:20 - 04:20pm:
Location: Gold Room

Jonathan P. Graf, "Ensuring Design Integrity through Analysis ..."

Jonathan P. Graf
Ensuring Design Integrity through Analysis of FPGA Bitstreams and IP Cores,
Jonathan P. Graf
Luna Innovations Inc., USA
Time: 11:20 - 12:20am:
Location: Gold Room

ERSA Invited Talks

Prof. Hiroaki Nishi "Future Internet Infrastructure and its ..."

Prof. Hiroaki Nishi
Future Internet Infrastructure and its Hardware Support Technology for Smart Grid,
Prof. Hiroaki Nishi,
Keio University, Japan
Time: 02:20 - 03:00pm:
Location: Gold Room

Prof. Pascal Benoit, "Distributed Approaches for Self-Adaptive ..."

Prof. Pascal Benoit
Distributed Approaches for Self-Adaptive Embedded Systems,
Prof. Pascal Benoit,
University of Montpellier, France
Time: 09:40 - 10:20am:
Location: Gold Room

Dr. Yohei Hori, "Tackling the Security Issues of FPGA..."

Dr. Yohei Hori
Tackling the Security Issues of FPGA Partial Reconfiguration with Physical Unclonable Function,
Dr. Yohei Hori,
National Institute of Advanced Science and Technology, Japan
Time: 10:40 - 11:20am:
Location: Gold Room