Dr Toomas P Plaks

Conference Chair
Dr Toomas P Plaks

London
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ERSA’12 PROGRAMME

ERSA REGULAR TALK

Dr.
From Streaming Models to FPGA Implementations,
Hugo Andrade, Jeff Correll, Amal Ekbal, Arkadeb Ghosal, Douglas Kim, Jacob Kornerup, Rhishikesh Limaye, Ankita Prasad, Kaushik Ravindran, Trung N Tran, Mike Trimborn, Gerald Wang, Ian Wong, Guang Yang,
National Instruments Corporation, USA
Time: 08:40 - 09:00am:
Location: Gold Room

Abstract:

Application advances in the signal processing and communications domains are marked by an increasing demand for better performance and faster time to market. This has motivated model-based approaches to design and deploy such applications productively across diverse target platforms. Dataflow models are effective in capturing these applications that are real-time, multi-rate, and streaming in nature. These models facilitate static analysis of key execution properties like buffer sizes and throughput. There are established tools to generate implementations of these models in software for processor targets. However, prototyping and deployment on hardware targets, such as FPGAs, are critical to the development of new applications. FPGAs are increasingly used in computing platforms for high performance streaming applications. Existing tools for hardware implementation from dataflow models are limited in their capabilities. To close this gap, we present DSP Designer, a framework to specify, analyze, and implement streaming applications on hardware targets. DSP Designer encourages a model-based design approach starting from a Parameterized Cyclo-Static Dataflow model. The back-end supports static analysis of execution properties and generates implementations for FPGAs. It also includes an extensive library of hardware actors and eases third-party IP integration. Overall, DSP Designer is an exploration framework that translates high-level algorithmic specifications to efficient hardware. In this paper, we illustrate the modeling, analysis, and implementation capabilities of DSP Designer. Through a detailed case study, we show that DSP Designer is viable for the design of next generation signal processing and communications systems.

Bio:

Hugo A. Andrade is a Principal Architect in the LabVIEW Group at National Instruments, where he has been employed since 1989. Hugo earned BS degrees in Electrical & Computer Engineering and Computer Sciences and an MS degree in Electrical & Computer Engineering from the University of Texas at Austin. While at National Instruments, among other projects, he has led standardization efforts on instrument control software, and led the research and early development of LabVIEW FPGA. He was a visiting industrial fellow at the University of California, Berkeley (2007-2008), and was the founding manager and tech lead of the NI Berkeley R&D site, where he currently works on advanced tools for system level design and synthesis to heterogeneous platforms, and serves as liaison to academic and industrial research labs in the area. Hugo holds over 50 patents in the areas of instrumentation software, hardware/software interfacing, reconfigurable computing, graphical programming, and system level design, and is a Ph.D. student in the Electrical and Computer Engineering department at the University of Texas at Austin under the guidance of Prof. Brian Evans, focusing his research on reliability aspects of heterogeneous, reconfigurable platforms.

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ERSA Distinguished Talks

Prof. Franz Richter, et al., "A Configurable VHDL Template for ..."

A Configurable VHDL Template for Parallelization of 3D Stencil Codes on FPGAs,
Franz Richter, Michael Schmidt and Dietmar Fey,
FAU Erlangen-Nuremberg, Germany
Time: 09:00 - 09:40am:
Location: Gold Room

Prof. Tim Gueneysu, "Cryptanalysis on Reconfigurable ..."

Dr.
Cryptanalysis on Reconfigurable Computers,
Tim Gueneysu,
Ruhr-Universitaet Bochum, Germany
Time: 03:20 - 03:40pm:
Location: Gold Room

Dr. Tomohiro Ueno, et al., "FPGA-based Implementation of ..."

FPGA-based Implementation of Compact Compressor and Decompressor of Floating-Point Data-Stream for Bandwidth Reduction,
Tomohiro Ueno, Yoshiaki Kono, Kentaro Sano, Satoru Yamamoto,
Tohoku University, Japan
Time: 04:40 - 05:20pm:
Location: Gold Room

Dr. Yoshiya Komatsu, et al., "Area-Efficeint Design of ..."

Area-Efficeint Design of Asynchronous Circuits Based on Balsa Framework for Synchronous FPGAs,
Yoshiya Komatsu, Masanori Hariyama And Michitaka Kameyama,
Tohoku University, Japan
Time: 04:00 - 04:40pm:
Location: Gold Room

ERSA Regular Talks

Yusuke Nishida, et al., "Implementation of a Hardware Architecture ..."

Implementation of a Hardware Architecture to Support High-speed Database Insertion on the Internet,
Yusuke Nishida, Hiroaki Nishi,
Keio University, Japan
Time:04:20 - 04:40pm:
Location: Gold Room

Elena Hammari, et al., "Identifying Data-Dependent System ..."

Dr.
Identifying Data-Dependent System Scenarios in a Dynamic Embedded System,
Elena Hammari*, Francky Catthoor**, Per Gunnar Kjeldsberg*, Jos Huisken***, Konstantinos Tsakalis****, Leonidas Iasemidis****,
* Norwegian University of Science and Technology, Norway
** Imec and K.U.Leuven, Belgium
*** Imec / Holst Centre, The Netherlands
**** Arizona State University, USA
Time:08:20 - 08:40am
Location: Gold Room

Hugo Andrade, et al., "From Streaming Models to FPGA ..."

Dr.
From Streaming Models to FPGA Implementations,
Hugo Andrade, Jeff Correll, Amal Ekbal, Arkadeb Ghosal, Douglas Kim, Jacob Kornerup, Rhishikesh Limaye, Ankita Prasad, Kaushik Ravindran, Trung N Tran, Mike Trimborn, Gerald Wang, Ian Wong, Guang Yang,
National Instruments Corporation, USA
Time: 08:40 - 09:00am:
Location: Gold Room

Yoichi Wakaba, et al., "A Practical FPGA Implementation ..."

A Practical FPGA Implementation of Regular Expression Matching with Look-ahead Assertion,
Yoichi Wakaba, Masato Inagi, Shin'ichi Wakabayashi,
Hiroshima City University, Japan
Time: 03:40 - 04:00pm:
Location: Gold Room

Retsu Moriwaki, et al., "Optical configuration acceleration on ..."

Optical configuration acceleration on a new optically reconfigurable gate array VLSI using a negative logic implementation,
Retsu Moriwaki and Minoru Watanabe,
Shizuoka University, Japan
Time: 05:20 - 05:40pm:
Location: Gold Room

Dr. Yoshiya Komatsu, et al., "Architecture of an Asynchronous FPGA ..."

Architecture of an Asynchronous FPGA for Handshake-Component-Based Design,
Yoshiya Komatsu, Masanori Hariyama and Michitaka Kameyama,
Tohoku University, Japan
Time: 05:40 - 06:00pm:
Location: Gold Room