Prof. David Andrews
Design Flows and Run Time Systems for Heterogeneous Multiprocessor Systems on Programmable Chips (MPSOPCS)
Prof. David Andrews,
University of Arkansas, USA
Time: 01:20 - 01:40pm
Location: Gold Room


Emerging platform FPGAs will contain over 1 million LUTs, enough to support hundreds of soft programmable cores. This level of integration opens the potential for designers to switch approaches for performance increases from tedious accelerator point designs to more portable and efficient software based scalable parallel processing. This also brings the use of platform FPGA's in line with modern heterogeneous manycore systems on chips. Clearly exciting, standardized design flows and programming models to enable designers to exploit this potential on platform FPGA's does not yet exist. To achieve true software-like levels of productivity, the design flow and development environment for heterogeneous MPSoCs must resemble that of standard homogeneous multiprocessor systems. In this talk we first present the challenges that must be addressed to creating appropriate design flows and run-time systems for heterogeneous MPSoPC's. We then present our approach to enable developers to guide the construction and program a heterogeneous MPSoC using standard POSIX-compatible programming abstractions. The ability to use a standard programming model is achieved by using a hardware-based microkernel to provide OS services to all heterogeneous components. This approach makes programming heterogeneous MPSoCs transparent, and can increase programmer productivity by replacing synthesis of custom components with faster compilation of heterogeneous executables. The use of a hardware microkernel provides OS services in an ISA-neutral manner, which allows for seamless synchronization and communication amongst heterogeneous threads.


David Andrews holds the Mullins Endowed Chair of Computer Engineering in the Computer Science and Computer Engineering (CSCE) Department at the University of Arkansas. Dr. Andrews received his B.S.E.E. and M.S.E.E. from the University of Missouri-Columbia and PhD in Computer Science from Syracuse University. He worked as a senior systems engineer and research scientist at General Electrics Electronics Laboratory and Advanced Technology Laboratory in Syracuse New York from 1985-1991 where he performed research for GE's Aerospace Business Group. During this time, he performed research on advanced signal processing systems including one of the first out of order execution dual fetch RISC microprocessors, and led the development of the operating system for the Seawolf submarine, a 128 node real time distributed message passing system. Since 1991, he has held faculty positions at the University of Kansas and University of Arkansas. His research interests are in the broad area of parallel computer architectures, operating systems, and programming models for real time and embedded systems.