has been held as an important part of WORLDCOMP:
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The international conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) was founded in 2001 and, since then, has been held each year in Las Vegas.
ERSA conference solicits papers from all aspects of reconfigurable computing, including classical programmable logic, as well as reconfigurable multiprocessing related papers. The topics of interests include theory, architecture, algorithms, design systems and applications that demonstrate the benefits of reconfigurable computing.
The topics of interest include, but are not limited to:
Topics of interest include but are not limited to:
ERSA conference will be composed of research presentations, keynote lectures, invited presentations, tutorials, panel discussions, and poster presentations.
Invited panel sessions consist of three parts:
All conference proceedings/books are considered for inclusion in major database indexes
Founder and Chair of ERSA Conference
Dr Toomas P Plaks
President and CEO of SRC Computers, LLC, Colorado Springs, USA
Looking Ahead at Heterogeneous Systems: A Suppliers Perspective.
In light of current processor chip architectures driving towards many-core and graphics, is there still a viable place for FPGA based computation? How much of the current information is hype and how much is doom for reconfigurable processing? ...
In 1996 Mr. Huppenthal, along with Seymour Cray, co-founded SRC Computers where Jon was the Chief Hardware Technologist and Vice President of Hardware Development. In that role he set the strategic direction and led the hardware design and integration efforts for the Company. ...Read more
Prof. Lotfi A. Zadeh
University of California, Berkeley, USA
Computing With Words and Perceptions - A Paradigm Shift
Dr. Firouz Naderi
Search for Life in the Universe
Prof. Rajkumar Buyya
The University of Melbourne, Australia
Cloud Computing: The Next Revolution in Information Technology
Better Languages for More Effective Designing
Washington University in St. Louis, USA
Developer productivity is strongly in uenced by the language(s) used during the design process. The abstraction level of the language as well as the opportunities for casual errors due to non-intuitive language features can both have a dramatic impact on developers. In this paper, we explore language design in three contexts: course-grained expression of parallelism, register transfer level hardware description languages, and specialized languages for particular purposes. ...
Roger D. Chamberlain is an associate professor in the Dept. of Computer Science and Engineering at Washington University in St. Louis. His research interests include specialized computer architectures for a variety of applications (e.g., astrophysics and biology), high-performance parallel and distributed application development, energy-efficient computation, and high-capacity I/O systems. He received his BSCS, BSEE, MSCS, and DSc degrees all from Washington University and is a member of IEEE and ACM. ...Read more
Next-Generation Networking Using FPGAs
University of Massachusetts, USA
Network infrastructure for the next generation Internet requires performance and flexibility which far exceeds today's infrastructure capabilities. The recent emergence of FPGAs in a variety of networking research platforms accentuates the promise of these reconfigurable devices for networking applications. In this talk, the state-of-the-art in FPGA-based networking platforms is described. ...
Russell Tessier Russell Tessier is an Associate Professor in the Department of Electrical and Computer Engineering at the University of Massachusetts, Amherst. ...Read more
Novo-G: A View at the HPC Crossroads for Scientific Computing
University of Florida, USA
High-performance computing for many science domains is at a major crossroads and in the center of a convergence of several technology megatrends of the last decade. First, technological advances in science areas such as genomics and astronomy have resulted in a growing gap between data production and the ability to analyze the data in a ...
Herman Lam is an Associate Professor at the Department of Electrical and Computer Engineering at the University of Florida, USA. He is a senior research member of the NSF Center for High-Performance Reconfigurable Computing (CHREC). ...Read more
A Dynamic Reconfigurable MRAM based FPGA
University of Montpellier 2, France
The work describes the integration of a thermally assisted switching magnetic random access memory (TAS-MRAM) in FPGA design. The non-volatility of the latter is achieved through the use of magnetic tunneling junctions (MTJ) in the MRAM cell. A thermally assisted switching scheme is used to write data in the MTJ device, ...
Lionel Torres , full Professor, obtained respectively his Master and PhD degree in 1993 and 1996 from the University of Montpellier 2 (France). From 1996 to 1997 he was in ATMEL company as IP core methodology R&D engineer. ...Read more
Effective integration of FPGAs into commercial high-performance computing (HPC) applications
CTO, Convey Computer
FPGAs can provide significant advantages in application performance while reducing space and power requirements. However, in the past they have often been difficult to program effectively or integrate into general-purpose or large clustered computing environments. Convey has developed a heterogeneous computing solution ...
Tony Brewer is the Chief Technology Officer of Convey Computer and is responsible for the technical strategy and direction of the company, including defining the architecture for Convey’s hybrid-core computer, the Convey HC-1. ...Read more
Submission of regular papers is open for everybody
More coming soon