ERSA’10
Las Vegas, Nevada, USA
July 12 - 15, 2010
The International Conference on
Engineering of Reconfigurable Systems and Algorithms
ERSA Conference
has been held as an important part of WORLDCOMP:
http://www.world-academy-of-science.org/
ERSA’10: Engineering of Reconfigurable Systems and Algorithms
The next ERSA’11 conference
ERSA’11 website is at:
http://ersaconf.org/ersa11
Introduction
The international conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) was founded in 2001 and, since then, has been held each year in Las Vegas.
ERSA conference solicits papers from all aspects of reconfigurable computing, including classical programmable logic, as well as reconfigurable multiprocessing related papers. The topics of interests include theory, architecture, algorithms, design systems and applications that demonstrate the benefits of reconfigurable computing.
General Topics
The topics of interest include, but are not limited to:
-
Theory of Massively Parallelel Computing
- Theoretical models of computing in space and time
- Theoretical approaches of new computational aspects, including biologically inspired approaches
- Adaptive computing
- Mapping algorithms into hardware and synthesis of regular arrays
- Parallelization and space-time partitioning of algorithms
- System architectures using configurable computing platform
-
Newly developed algorithms for efficient implementation on reconfigurable systems
-
Software, CAD and Operating Systems
- CAD, specification, partitioning and verification
- Hardware compilation, hardware/software codesign, developing correct circuits
- High and low-level languages and compilers, design environments
- Operating systems and run-time reconfiguring
-
IP-based and object oriented models and mapping methods
-
Adaptive Hardware Architectures
- Adaptive and dynamically reconfigurable systems
- Reconfigurable processor architectures
- Complex systems using reconfigurable processors
- Application-tailored reconfigurable Systems-on-Chip
-
Energy efficient systems on reconfigurable computing platform
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Applications
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Wireless communication systems
Mobile communication systems, videophone, software radio, global positioning systems etc.
-
Multimedia and virtual reality
Video imaging, teleconferencing, data compression, image databases, computational geometry and computer graphics etc.
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Automotive industry
Vehicle guidance, lane and obstacle detection, object recognition, traffic systems, navigation of robots etc.
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Security systems
Object recognition and tracking, cryptology, Internet and security etc.
-
Classical image and signal processing
Digital filters, edge and line detection, morphological operators, motion and stereo estimation, discrete transformations, linear algebra, radar systems, object recognition etc.
-
Wireless communication systems
Topics of interest include but are not limited to:
- Theory - Synthesis, Mapping, Parallelization, Partitioning...
- Software - CAD, Languages, Compilers, Operating Systems...
- Hardware - Adaptive and Dynamic Hardware, Reconfigurable Architectures...
- Applications - Mobile Computing, Automotive Industry, Smart Cameras...
ERSA conference will be composed of research presentations, keynote lectures, invited presentations, tutorials, panel discussions, and poster presentations.
Invited panel sessions consist of three parts:
- Invited paper presentations
- Panel discussion
- Regular session that relates to the panel session topics, open submission.
Hot Topics
- Reconfigurable and Evolvable Hardware Architecture
- Parallelism and Reconfigurable Multi-Core Systems
- Dynamic Partial Runtime Reconfiguration
- Design Tools, Design Flow , Dynamic Architectures, Scheduling
- Runtime Resource Management: Processes, Processors And Communication
- Energy-Efficient Reconfigurable Mobile Systems
- Applications, Embedded Systems, Security, Image And Signal Processing
- Emerging Applications
All conference proceedings/books are considered for inclusion in major database indexes
Making references to ERSA Making references to ERSA papers
To refer to (cite) this publication or any particular paper/article in this publication, the following style should be used:
[Name of authors of the paper being cited];
[Title of paper being cited],
Proceedings of 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms
(ERSA’06/ISBN #:1-60132-011-6/CSREA),
Editor: Toomas P. Plaks
pp.:[page numbers (inclusive)], Las Vegas, USA, 2006.
Copyright Policy Copyright Policy
The authors have no restrictions to use their ERSA papers.
However, when they do post their articles, they must acknowledge the publication by adding the following text:
• The article was originally published in the book referenced below:
• ISBN #: (for example: 1-60132-140-6)
• TITLE: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'##)
• EDITOR: Toomas P. Plaks
• ASSOCIATE EDITORS: list the associated editors of this year
• URL: http://www.world-academy-of-science.org/
and http://ersaconf.org/ersa##
(where the ## is the year of ERSA conference: 06, 07, 08, 09, 10, ...)
Founder and Chair of ERSA Conference
Dr Toomas P Plaks
London
Recipient of ERSA/WORLDCOMP 2010 Award
OUTSTANDING ACHIEVEMENT AWARD
Jon Huppenthal
President and Chief Executive Officer, SRC Computers, LLC
Co-Founder (with Late Seymour Cray)
In Recognition of his Leadership, Outstanding Research &
Technical Contributions to the field of Heterogeneous Systems
WORLDCOMP Keynotes
from ERSA’10
Jon Huppenthal
President and CEO of SRC Computers, LLC, Colorado Springs, USA
Looking Ahead at Heterogeneous Systems: A Suppliers Perspective.
Abstract:
In light of current processor chip architectures driving towards many-core and graphics, is there still a viable place for FPGA based computation? How much of the current information is hype and how much is doom for reconfigurable processing? ...
BIO
In 1996 Mr. Huppenthal, along with Seymour Cray, co-founded SRC Computers where Jon was the Chief Hardware Technologist and Vice President of Hardware Development. In that role he set the strategic direction and led the hardware design and integration efforts for the Company. ...
Read moreFeatured
Prof. Lotfi A. Zadeh
University of California, Berkeley, USA
Computing With Words and Perceptions - A Paradigm Shift
Dr. Firouz Naderi
CalTech/NASA, USA
Search for Life in the Universe
Prof. Rajkumar Buyya
The University of Melbourne, Australia
Cloud Computing: The Next Revolution in Information Technology
ERSA’10 Keynotes
-
Prof. Roger Chamberlain
Better Languages for More Effective Designing
Washington University in St. Louis, USAAbstract:
Developer productivity is strongly in uenced by the language(s) used during the design process. The abstraction level of the language as well as the opportunities for casual errors due to non-intuitive language features can both have a dramatic impact on developers. In this paper, we explore language design in three contexts: course-grained expression of parallelism, register transfer level hardware description languages, and specialized languages for particular purposes. ...
BIO
Roger D. Chamberlain is an associate professor in the Dept. of Computer Science and Engineering at Washington University in St. Louis. His research interests include specialized computer architectures for a variety of applications (e.g., astrophysics and biology), high-performance parallel and distributed application development, energy-efficient computation, and high-capacity I/O systems. He received his BSCS, BSEE, MSCS, and DSc degrees all from Washington University and is a member of IEEE and ACM. ...
Read more -
Prof. Russell
Tessier
Next-Generation Networking Using FPGAs
University of Massachusetts, USAAbstract:
Network infrastructure for the next generation Internet requires performance and flexibility which far exceeds today's infrastructure capabilities. The recent emergence of FPGAs in a variety of networking research platforms accentuates the promise of these reconfigurable devices for networking applications. In this talk, the state-of-the-art in FPGA-based networking platforms is described. ...
BIO
Russell Tessier Russell Tessier is an Associate Professor in the Department of Electrical and Computer Engineering at the University of Massachusetts, Amherst. ...
Read more -
Prof. Herman
Lam
Novo-G: A View at the HPC Crossroads for Scientific Computing
University of Florida, USAAbstract:
High-performance computing for many science domains is at a major crossroads and in the center of a convergence of several technology megatrends of the last decade. First, technological advances in science areas such as genomics and astronomy have resulted in a growing gap between data production and the ability to analyze the data in a ...
BIO
Herman Lam is an Associate Professor at the Department of Electrical and Computer Engineering at the University of Florida, USA. He is a senior research member of the NSF Center for High-Performance Reconfigurable Computing (CHREC). ...
Read more -
Prof. Lionel
Torres
A Dynamic Reconfigurable MRAM based FPGA
University of Montpellier 2, FranceAbstract:
The work describes the integration of a thermally assisted switching magnetic random access memory (TAS-MRAM) in FPGA design. The non-volatility of the latter is achieved through the use of magnetic tunneling junctions (MTJ) in the MRAM cell. A thermally assisted switching scheme is used to write data in the MTJ device, ...
BIO
Lionel Torres , full Professor, obtained respectively his Master and PhD degree in 1993 and 1996 from the University of Montpellier 2 (France). From 1996 to 1997 he was in ATMEL company as IP core methodology R&D engineer. ...
Read more -
Tony Brewer
Effective integration of FPGAs into commercial high-performance computing (HPC) applications
CTO, Convey ComputerAbstract:
FPGAs can provide significant advantages in application performance while reducing space and power requirements. However, in the past they have often been difficult to program effectively or integrate into general-purpose or large clustered computing environments. Convey has developed a heterogeneous computing solution ...
BIO
Tony Brewer is the Chief Technology Officer of Convey Computer and is responsible for the technical strategy and direction of the company, including defining the architecture for Convey’s hybrid-core computer, the Convey HC-1. ...
Read more
Invited Panel Sessions
Submission of regular papers is open for everybody
-
Signal-Image Processing
and Dynamic Partial ReconfigurationSignal-Image Processing and Dynamic Partial Reconfiguration
Ronald F. DeMara and Jooheung Lee
School of Electrical Engineering and Computer Science
University of Central Florida, USAAbstract
Many signal processing applications traditionally implemented in ASICs are increasingly choosing FPGA solutions due to factors such as reduced cost, improved ease of design changes, and faster time-to-market. Today’s dynamic partial reconfiguration capabilities of FPGAs motivate architectural innovations
Read more -
Reconfigurable Supercomputing: Performance, Productivity, and Sustainability
Reconfigurable Supercomputing: Performance, Productivity, and Sustainability
Herman Lam and Greg Stitt
CHREC
University of Florida, USAAbstract
Reconfigurable computing (RC) using FPGAs has been widely known to have significant performance advantages compared to microprocessors, in some cases achieving speedup ranging from 10x to 10000x. By combining these performance advantages
Read more Processor Customization for Reconfigurable Fabrics
Processor Customization for Reconfigurable Fabrics
David Andrews* and Christian Plessl**
*Univ. of Kansas, USA
** Paderborn Center for Parallel Computing
University of Paderborn, GermanyAbstract
Since the inception of reconfigurable computing researchers have sought new approaches to exploit the ability to form customized processor and computational units within the hardware fabric.
Read more
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