ERSA’2009
The International Conference on
Engineering of Reconfigurable Systems and Algorithms

Future Multi-Core System-on-Chip (MCSoC): Adaptive and Reliable Computing in the Nano Era

Prof. Juergen Becker, Karlsruhe Institute of Technology - KIT, Germany

The field of parallel embedded electronic systems is still emerging. Multipurpose adaptivity and reliability features are playing more and more of a central role, especially while scaling silicon technologies down according to Moore´s benchmarks. Leading processor and mainframe companies are gaining more awareness of reconfigurable computing technologies due to increasing energy and cost constraints. My view is of an “all-win-symbiosis” of future silicon-based processor technologies and parallel multi-core as well as reconfigurable circuits/architectures. Dynamic and partial reconfiguration has progressed from academic labs to industry research and development groups, providing high adaptivity for a range of applications and situations. Reliability, failure-redundancy and run-time adaptivity using real-time hardware reconfiguration are important aspects for current and future systems. Thus, scalability, as we have experienced for the last 35 years is at its end as we enter the so-called Nano Era. Beyond the capabilities of traditional reconfigurable fabrics (like FPGAs), nano circuits/architectures allow for micro-mechanical switches that enable new memory and reconfiguration technologies with the advantage of online chip adaptivity and non-volatility. The deployment of new 3-D nano structures and materials promises higher integration densities and is considered advantageous for signal delays. Yield is significantly lower, and could, as we define it in the classical sense, eventually be nil! Transient faults may lead to unreliable information processing as information in nano-sized devices is much less. Power consumption and related problems present a challenge where information is processed within a smaller area/volume budget. Thus, novel design methodologies, novel adaptive mechanisms which solve operation-time shortcomings, and novel computing paradigms are necessary. Fault tolerance/correction in all its facets is key and should be considered an inherent technique in any nano design/synthesis step. This keynote will discuss the corresponding challenges and outline some arising perspectives for future multi-core and adaptive as well as reliable systems-on-chip (MCSoC), for application-tailored embedded and general purpose systems.

Jürgen Becker is Full Professor for Embedded Electronic Systems in the department of Electrical Engineering and Information Technology at Universität Karlsruhe (TH). His actual research is focused on industrial-driven System-on-Chip (SoC) integration with emphasis onadaptivity, e.g. dynamically re-configurable hardware architecture development and application in automotive and communication systems. Prof. Becker is Head of the Institute for Information Processing (ITIV) and Department Direc-tor of Electronic Systems and Microsystems (ESM) at the Computer Science Research Center (FZI). From 2001- 2005 he has been Co-Director of the International Department at Universität Karlsruhe (TH). He is author and co-author of more than 180 scientific papers, and active as general and technical program chairman of national / international conferences and workshops. He is executive board member of the german IEEE section, Board member of the GI/ITG Technical Committee of Architectures for VLSI Circuits, Associate Editor of the IEEE Transactions on Computers, and Senior Member of the IEEE. Since October 2005 Prof. Becker is Vice-President ("Prorektor") for Studies and Teaching at Universität Karlsruhe (TH).