Conference Programme

Invited Talks

  • Prof. Christophe Jego Prof. Christophe Jego, ENST Bretagne, France
    FPGA prototyping approach for the validation of efficient iterative receivers in digital communication systems

    The turbo principle is a general way of processing data in receivers so that no information is wasted. This technique corresponds to an iterative exchange of soft information between different blocks in a communications receiver in order to improve overall system performance. It has opened up a new way of thinking in the construction of communication algorithms. This method was introduced in a system of error control for data transmission in 1993, called turbo code. This family of Forward Error Codes (FEC) consists of two key design innovations: ...
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  • Prof. Hideharu Amano Prof. Hideharu Amano, Keio University, Japan
    The 2nd Generation Japanese Dynamically Reconfigurable Processors

    Dynamically Reconfigurable Processors have been started to be utilized as an off-load engine for various types of System-on-Chips (SoCs) in digital appliances. In order to achieve better area- and power-efficiency compared with traditional field-programmable devices such as FPGAs, they incorporate the following properties; (1) a simple coarse grained processor consisting of an ALU, a data manipulator, ...
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  • Prof. Christophe Wolinski Prof. Christophe Wolinski, University of Rennes I, France
    Prof. Krzysztof Kuchcinski, Lund University, Sweden
    Kevin Martin, University of Rennes I, France
    Erwan Raffin, Thomson Corporate Research, Rennes, France
    Francois Charo, University of Rennes I, France
    How constrains programming can help you in the generation of optimized application specific reconfigurable processor extensions

    We present different tasks from the generic design flow that is used to identify and select computational patterns as well as map applications and schedule them on processors with extensions implementing these patterns. The distinctive feature of our approach is that all design tasks are completely specified and solved using constraints programming with specially developed graph constraints. Therefore our approach is very flexible and makes possible to easily include new design constraints. Our design flow automatically creates functionally reconfigurable processor extensions implementing different architectural models. The selected processor extensions are...
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  • Prof. TBA TBA,

    Abstract: Coming soon ... ...

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