Conference Programme

Demos & Panels & Tutorials & ...

Back to ERSA Panel

Panel Discussion

Next Generation Research Challenges in Reconfigurable Computing

Follows after respective Technical Session
Read more ...

Prof. David Andrews Moderator:

Prof. David Andrews, University of Kansas, USA
Modeling Abstractions for Next Generation Reconfigurable Computing
David Andrews, Jason Agron
University of Kansas, USA

In this paper we outline the need for new research in virtual computational models for next generation reconfigurable computing platforms. Virtual computational models form an abstract representation of a machines primitive capabilities. Modern virtual computational models are formed through a combination of high level languages, middleware and operating system services. Virtual computational models enable portability across hardware computing platforms. Creating such a virtual computational model for reconfigurable systems is a difficult challenge as it will require researchers to stretch beyond the accepted approaches of treating the reconfigurable fabric as a simple co-processor accelerator and revisit many of the unsolved problems from the prior parallel processing era. This challenge is also shared with the evolving manycore movement which seeks to create new approaches to enable systems with 1,00’s and 1,000’s of cores that seamlessly integrate both coarse grained multithreaded as well as fine grained data parallelism programming models.
Read more ...

Panel Members:

  • Prof. Gordon Brebner Prof. Gordon Brebner Xilinx Research Laboratories, San Jose, CA, USA
    Reconfigurability: Finding The Problems That Need The Solution

    This talk concerns the desirability (or otherwise) of a broad research activity in the area of “dynamically adaptable behaviors”, seeking to explore the full potential of reconfigurable technologies such as FPGAs. The aim would be to investigate the capabilities of existing silicon architectures from an application centered perspective, the driving question being whether it is natural or useful to incorporate dynamically adaptable behavior into an application’s implementation. This looks like a natural focal point, given the immense capabilities of the contemporary silicon, and particularly now that over a decade’s research into general-purpose dynamic reconfiguration (often without immediate applications) has reached maturity. Rather than devise ad hoc solutions on an application by application basis, an objective would be to interpret the notion of dynamically adaptable behaviors for fairly broad application domains, consistently with trends in domain-specific programming languages. The talk will be illustrated by examples related to experimental tools for the networking and telecommunications domain. The intention is to promote discussion about future research directions.
    Read more ...
  • Prof. Ryan Kastner Prof. Ryan Kastner, University of California San Diego, CA, USA
    Threats and Challenges in Reconfigurable Security
    Ryan Kastner*, Ted Huffmire**
    *University of California, San Diego, USA
    **Naval Postgraduate School, Monterey,USA

    Computing systems designed using reconfigurable hardware are now used in many sensitive applications, where security is of utmost importance. Unfortunately, a strong notion of security is not currently present in FPGA hardware and software design flows. In the following, we discuss the security implications of using reconfigurable hardware in sensitive applications, and outline problems, attacks, solutions and topics for future research.
    Read more ...

  • Prof. Brent E Nelson Prof. Brent E Nelson, Brigham Young University, USA
    Design Productivity for Configurable Computing
    Brent Nelson*, Michael Wirthlin*, Brad Hutchings*, Peter Athanas**, Shawn Bohner**
    *Brigham Young University, USA
    **Virginia Tech., USA

    Like design productivity for ASIC design, design productivity for FPGA design suffers from the well-known design productivity gap -- silicon densities continue to double every 1.5 to 2 years while design capabilities are growing at a much slower rate. Just to keep from falling behind in the future, design productivity must improve according to Moore’s Law. However, based on the historical pace of design methods and tools for hardware design, this is highly unlikely without significant focused effort by the research community.
    Read more ...

  • Prof. Bernard Pottier Prof. Bernard Pottier, University of Bretagne Occidentale, France
    FPGA or Distributed Systems ?

    Reconfigurable devices are following the integration progresses and today solutions can be classified according to the weight of reconfigurability support:
    • FPGA market: these circuits support flexibility through logic synthesis but are no more restricted to this field. Largest FPGAs include coarse grain circuits (operators, memories), multicores, and can allow partial reconfiguration.
    • SoC based reconfigurability: these circuits are inherently custom and tuned for particular applications. The novelty is that they can include reconfigurable banks with system support for reconfiguration and data feeding.
    Read more ...

  • John Watson John Watson, VP of ElementCXI, CA, USA
    A New Tact in Reconfigurable Computing Research
    J. Watson, S. Kelem, B. Box, J. Hassoun, S. Wasson, R. Plunkett, C. Phillips
    Element CXI, Milpitas, CA, USA

    For the most part, reconfigurable architectures have been based on existing IC architectures or combinations of them. To date, they have lukewarm success at best. A fundamentally different thought process is needed to unleash the value of adapting hardware to the problem at hand. One that delivers on the promise of super-computer performance on battery power at consumer price points to replace ASIC, SOC, FPGA and multi-processor solutions. Every engineer understands the definition of work as W=F*D Cos Θ. This is the definition used in physics. But, when asked what the definition of work is in electronic circuits you get a blank stare followed by, “ it must have something to do with energy, MHz, bus width, etc.” In other words, you do not receive a credible answer. This paper explores a few research concepts and opportunities in regards to a definition of work in electronics and its implication in the definition of reconfigurable architectures. Read more ...

Industrial Workshop

Synplicity®, Inc. Synplicity®, Inc., USA

Architectural Synthesis for Reconfigurable Computing

Chris Eddington Speaker: Chris Eddington, Synplicity®, Inc., USA

One of the challenges for reconfigurable computing is the effort required to map algorithms into efficient hardware architectures that meet goals for timing, area, and power. High Level Synthesis (HLS) techniques can automate this process, however they face formidable challenges. Part of the problem is that HLS techniques are very dependent on the capabilities of the target technology which burdens the tools and complicates the optimization search. Another problem is in the algorithm expression or specification. Many popular design languages can be incomplete in the specification of timing and/or precision, or they make assumptions about the underlying ...
Read more ...

Night Lightning