ERSA’2007
The International Conference on
Engineering of Reconfigurable Systems and Algorithms

Las Vegas, Nevada, USA, June 25 - 28, 2007


ERSA’07 Final Programme

Time Schedule

Schedule in ASCII

See also NEWS.

ERSA’07 Accepted Papers

WORLDCOMP’07 Keynote from ERSA

  1. Steve Leibson, Tensilica, Inc., USA
    Challenges in Consumer Electronics for 21st Century

    Monday: 10:55 - 11:55 am
    Room: Lance Burton Theatre

ERSA’07 Keynotes

  1. Scientific Computing Using Reconfigurable Hardware
    Prof. Viktor K. Prasanna, Univ. of Southern California, USA

    Wednesday: 11:00 - 11:45am
    Room: Gold Room
  2. Novel Uses of Memory for Adaptive Power-down in FPGAs
    Prof. John Villasenor, Univ. of California Los Angeles, USA

    Monday: 01:15 - 02:00am
    Room: Gold Room

ERSA’07 Invited Talks

  1. A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays - Case Study and Quantitative Evaluation
    Prof Jürgen Teich, Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Dmitrij Kissler, and Andrej Stravet
    Univ. of Erlangen-Nürnberg, Germany

    Tuesday: 10:40 - 11:25am
    Room: Gold Room
  2. An Integrated Platform For Heterogeneous Reconfigurable Computing
    Dr Bernard Pottier, Jalil Boukhobza and Thierry Goubier
    Univ. of Bretagne Occidentale, France

    Tuesday: 11:30 - 12:15am
    Room: Gold Room

ERSA’07 Distinguished Papers

  1. Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAs
    Jens Hagemeyer, Boris Kettelhoit, Markus Köster, Mario Porrmann
    University of Paderborn, Germany

    Full Paper
  2. Design Space Exploration of Multiprocessor Systems with MultiContext Reconfigurable Co-Processors
    Pranav Vaidya, Jaehwan John Lee
    Purdue University, USA

ERSA’07 Regular Papers

  1. Memory Hierarchy for MCSoPC Multithreaded Systems
    Erik Anderson, Wesley Peck, Jim Stevens, Jason Agron, Fabrice Baijot, Seth Warn, David Andrews
    University of Kansas, USA
  2. Computation Patterns Identification for Instruction Set Extensions Implemented as Reconfigurable Hardware
    Christophe Wolinski *, Krzysztof Kuchcinski **
    *IRISA, IFSIC, France
    **Lund University, Sweden
  3. HW implementation of a task manager for reconfigurable systems.
    Javier Resano, Juan Antonio Clemente, Carlos Gonzalez, Jose Luis Garcia, Daniel Mozos
    Universidad Complutense de Madrid, Spain
  4. Power Efficient Domain-Specific Reconfigurable Architectures for System-on-Chip Applications
    Arjun K Pai and Khaled Benkrid
    Queen's University Belfast, United Kingdom
  5. Pure ASIC-based Retargetable Computing: Architectures, Advantages, and Challenges
    Yong-Kyu Jung
    Texas A&M University, USA
  6. Reducing Critical Path Delay in FPGAs with SRAM Tables Shared by NPN-Equivalent Functions
    Jason J. Meyer and Fatih Kocan
    Southern Methodist University, USA
  7. Selecting Heterogeneous Computation Blocks for Reconfigurable JPEG Codec Computing
    Wei-Ting Wang, Wai-Hong Tam, Yi-Chi Chen, Kuen-Cheng Chiang, Chung-Ping Chung
    National Chiao Tung University, Taiwan, ROC
  8. 272 gate count optically differential reconfigurable gate array VLSI.
    Minoru Watanabe, Takenori Shiki, and Fuminori Kobayashi
    Kyushu Institute of Technology, Japan
  9. Task Partitioning for the Scheduling on Reconfigurable Systems driven by Specification Self-Similarity
    Matteo Giani, Massimo Redaelli, Marco D. Santambrogio, Donatella Sciuto
    Politecnico di Milano, Italy
  10. High Efficiency Protection Solution for Off-Chip Memory in Embedded Systems
    Romain Vaslin *, Guy Gogniat *, Jean-Philippe Diguet * Russell Tessier**, Wayne Burleson**
    *LESTER - Centre de recherche, France
    **University of Massachusetts, USA
  11. Simulation Framework for Performance Prediction in the Engineering of Reconfigurable Systems and Applications
    Eric Grobelny, Casey Reardon, Adam Jacobs, and Alan D. George
    University of Florida, USA
  12. Prototyping of a Two-Phase Micropipeline on FPGAs
    Abdel Ejnioui
    University of South Florida, USA
  13. Configuration and Data Scheduling for Executing Dynamic Applications onto Multi-Context Reconfigurable Architectures
    F. Rivera, M. Sanchez-Elez, N. Bagherzadeh
    Depto. Arquitectura de Computadores y Automatica, Spain
  14. Energy-Efficient Dynamic Task Scheduling Algorithm for Reconfigurable System-on-Chip Architectures
    Swathi T. Gurumani, B. Earl Wells
    The University of Alabama in Huntsville, USA
  15. Latency Optimization for a Reconfigurable, Self-Timed, and Bit-Serial Architecture
    Achim Rettberg, Florian Dittmann, Raphael Weber
    University Paderorn, Germany
  16. An FPGA Implementation of Reciprocal Sums for SPME
    Sam Lee, Paul Chow
    University of Toronto, Canada
  17. A Compiler to Generate Hardware from Java Byte Codes for High Performance, Low Energy Embedded Systems
    Darrin Hanna, Michael DuChene, Lawrence Kennedy, and Brian Carpenter
    Oakland University, USA
  18. High-Precision BLAS on FPGA-enhanced Computers
    Chuan He*, Guan Qin*, and Richard E. Ewing*, Wei Zhao**
    *Texas A&M University, USA
    **Rensselaer Polytechnic Institute, USA
  19. Optimization of Shared High-Performance Reconfigurable Computing Resources
    Melissa C. Smith *, Gregory D. Peterson **,
    * Clemson University, USA
    ** University of Tennessee, USA
  20. FPGA Implementation of Analytic Design Method for a Cycle-Optimal 2-D DCT/IDCT
    Michaela E. Amoo and Clay S Gloster, Jr.
    Howard University, Washington, DC, USA
  21. Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors
    Xiaofang Wang, Sotirios G Ziavras, Jie Hu
    New Jersey Institute of Technology, USA
  22. Feasibility of Hardware Acceleration of a Neocortex Model
    Sébastien Lafontant*, Tarek M. Taha**
    *IBM, USA
    ** Clemson University, USA
  23. A Scalable and Reconfigurable Shared-Memory Graphics Cluster Architecture
    Ross Brennan and Michael Manzke and Keith O'Conor and John Dingliana and Carol O'Sullivan
    Trinity College Dublin, Ireland
  24. Efficient FPGA based Implementation of Time and Frequency Synchronization for MIMO-OFDM
    Jeoong Sung Park*, Hong Jip Jung**
    *Silicon Image Inc. Sunnyvale, CA, USA
    **Samsung Electronics, Seoul, Korea

ERSA’07 Short Papers

  1. Reducing the reconfiguration overhead: a survey of techniques
    Elena Pérez-Ramo*, Javier Resano*, Daniel Mozos*, Francky Catthoor**
    *Universidad Complutense de Madrid, Spain
    **Katholieke Universiteit Leuven, Belgium
  2. Implementing The G.723.1 Speech Codec Using A Coarse-Grained Reconfigurable Coprocessor
    Henrik Svensson, Thomas Lenart and Viktor Öwall
    Lund University, Sweden
  3. Exploring Partial Reconfiguration for Mitigating SEU faults in SRAM-Based FPGAs
    Cristiana Bolchini, Fabio SAlice, Marco D. Santambrogio
    Politecnico di Milano, Italy
  4. Performance analysis of Multi-process execution model on Dynamically Reconfigurable Processor
    Vu Manh Tuan, Yohei Hasegawa, and Hideharu Amano
    Keio University, Japan
  5. Agent-Based Reconfigurability for Fault-Tolerance in Network-on-Chip
    Pekka Rantala, Jouni Isoaho, Hannu Tenhunen
    University of Turku, Finland
  6. Design and Evaluation of a Software Infrastructure for the Runtime Management of Reconfigurable Resources
    Dimitris Syrivelis, Spyros Lalis
    Dept of Computer Engineering and Communications, Greece
  7. Evolvable Hardware: a functional level evolution framework based on ImpulseC
    Anna Antola, Marco Castagna, Pamela Gotti, David Pellerin, Marco D. Santambrogio
    Politecnico di Milano, Italy
  8. Autonomous Computing Systems: A Proposed Roadmap
    Neil Steiner and Peter Athanas
    Virginia Polytechnic Institute and State University, USA
  9. FPGA Implementation of a Reconfigurable License Plate Detection Method
    Ludek Bryan, Otto Fucik
    FIT BUT Brno, Czech Republic
  10. Performance Evaluation of Two Allocation schemes for Combinatorial Group Testing Fault Isolation Method
    Rawad N. Al-Haddad, Carthik A. Sharma and Ronald F. DeMara
    University of Central Florida, USA
  11. High-Level Specification of Runtime Reconfigurable Designs
    Stephen D. Craven, Peter M. Athanas
    Virginia Polytechnic Institute and State University, USA
  12. Optimization of reconfiguration speed control bits for an Optically Reconfigurable Gate Array
    Minoru Watanabe
    Shizuoka University, Japan
  13. Autonomous Computing Systems: A Proof-of-Concept
    Neil Steiner and Peter Athanas
    Virginia Polytechnic Institute and State University, USA

ERSA’07 Posters

  1. A TCP/IP Fragmentation Monitoring Core For Intrusion Prevention
    Vukasin Pejovic, Slobodan Bojanic and Carlos Carreras
    Universidad Politecnica de Madrid, Spain

Luxor



WORLDCOMP events of ERSA interest


Tutorials


Prof. H. J. Siegel
Colorado State Univ., USA

Robust Resource Allocation for Heterogeneous Parallel and Distributed Computing Systems

Monday: 6:00-9:00 pm
Room: Ballroom 6


Prof. Nasser Kehtarnavaz
Univ. of Texas at Dallas, USA

Real-Time Image and Video Processing: From Research to Reality

Tuesday: 6:00-9:30 pm
Room: Ballroom 1


Dr. Henk Wymeersch
MIT, USA

Factor Graphs for Advanced Algorithm Design in Wireless Communications

Wednesday: 6:00-9:30pm
Room: Ballroom 2


Photo not available

Prof. Ray Kresman
Bowling Green State University, USA

Cryptographic Features and Applications in Java (and C++)

Wednesday: 6:00-9:30pm Room: Ballroom 4


Conferences





Conference Chair
Dr Toomas P Plaks

London
Contact the Conference Chair


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