ADN Technical & Research Papers

Fadi Obeidat
Embedded Processor Selection Using FPGA-based Profiling
Fadi Obeidat* and Robert H. Klenke**
* Intel Corporation, Austin, TX, USA
** ECE Department, Virginia Commonwealth University, Richmond, Virginia, USA
ADN Issue 2, Nov 2013

Abstract

In embedded systems, modeling the performance of off-the-shelf processors is very important to enable the designer to estimate the capability of each candidate processor against the target application. Considering the large number of available embedded processors, the need has increased for building an infrastructure by which it is possible to estimate the performance of a given application on a certain processor with a minimum of time and resources. This paper presents the use a Xilinx MicroBlaze softcore processor ...

J. Paul Morrison
Flow-Based Programming
J. Paul Morrison
J.P. Morrison Enterprises Ltd., Unionville, Ontario, Canada
ADN Issue 1, Mar 2013

Abstract

In this paper, we give a short description of an application development technology called Flow-Based Programming (FBP), briefly describing its basic concepts, history, and some of our experience with it. An early implementation of FBP has been in continuous production use for almost 40 years, but it is attracting attention world-wide as it is a significant and important paradigm in building and maintaining computer applications.

Lindsay Black
High Performance Computing for Scientific and Technical Applications. A brief history and reality today
Lindsay M Black
MIET, MIEEE
ADN Issue 1, Mar 2013

Abstract

This paper is intended to be an unbiased and high level view of HPC history covering experiences learnt by suppliers and end users in this specialist area of technology. The paper will also give a personal view of the issues HPC faces today.

The HPC market knowledge presented in this paper covers: Aerospace, Defence, Government, Life Sciences, Manufacturing, Financial Services, General Research, Oil & Gas, Pharmaceutical & Chemical, Weather Prediction and many in-house developed codes for specific applications.

Brian Durwood
High Level Design of Hardware-based, Low-Latency Filters for “Big Data”
Brian Durwood*, Edward Trexel* and Alan Coppola**
*Impulse Accelerated Technologies Inc, USA
**OptNgn Software, USA
ADN Issue 1, Mar 2013

Abstract

In this paper we present an analysis of how the growth of data sets has funded the development of hardware accelerated data filters. The hardware of choice in 2012/2013 appears to be field programmable gate arrays due to their inherent flexibility in I/O configuration and the ability to parallelize algorithms intended originally for CPU, to refactor them for optimal functionality in FPGA. The article assumes expertise in data but only moderate familiarity with tools and techniques for handling field programmable gate arrays. The authors strive to a realistic assessment of the new methodologies with sensitivity to the (occasionally significant) differences with the compilation path involved in contrast to CPU or GPU compilation.

Parlament, London

Parlament,
London, United Kingdom

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