ADN Issue 6, May 2014

Contents

Embedded Software

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Optimizing embedded software for power efficiency: Part 1 - measuring power
Rob Oshana* and Mark Kraeling**
*Freescale Semiconductor, **General Electric
Embedded, May 11, 2014
One of the most important considerations in the product lifecycle of an embedded project is to understand and optimize the power consumption of the device. Power consumption is highly visible for hand-held devices which require battery power to be able to guarantee certain minimum usage/idle times between recharging. Other embedded applications, such as medical equipment, test, measurement, media, and wireless base stations, are very sensitive to power as well -- due to the need to manage the heat dissipation of increasingly powerful processors, power supply cost, and energy consumption cost -- so the fact is that power consumption cannot be overlooked.

Tags: Embedded, Software,
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Optimizing embedded software for power efficiency: Part 2 - Minimizing hardware power
Rob Oshana* and Mark Kraeling**
*Freescale Semiconductor, **General Electric
Embedded, May 11, 2014
Data flow optimization focuses on working to minimize the power cost of utilizing different memories, buses, and peripherals where data can be stored or transmitted by taking advantage of relevant features and concepts. Algorithmic optimization refers to making changes in code to affect how the cores process data, such as how instructions or loops are handled.

Hardware optimization, as discussed here, focuses more on how to optimize clock control and power features provided in the microprocessor or peripheral circuits.

Tags: Embedded, Software,
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Optimizing embedded software for power efficiency: Part 3 - Optimizing data flow and memory
Rob Oshana* and Mark Kraeling**
*Freescale Semiconductor, **General Electric
Embedded, May 11, 2014
Because clocks in an embedded system design have to be activated not only in the core components, but also in buses and memory cells, memory-related functionality can be quite power-hungry, but luckily memory access and data paths can also be optimized to reduce power.

Common practice is to optimize memory in order to maximize the locality of critical or heavily used data and code by placing as much in cache as possible. Cache misses incur not only core stall penalties, but also power penalties as more bus activity is needed, and higher-level memories (internal device SRAM, or external device DDR) are activated and consume power. As a rule, access to higher-level memory such as DDR is not as common as internal memory accesses, so high-level memory accesses are easier to plan, and thus optimize.

Tags: Embedded, Software,
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Optimizing embedded software for power efficiency: Part 4 - Peripheral and algorithmic optimization
Rob Oshana* and Mark Kraeling**
*Freescale Semiconductor, **General Electric
Embedded, May 11, 2014
When considering the impact of reading and writing of data has on an embedded system’s power utilization we cannot just think about memory access: we need to pull data into and out of the device as well. Here we will we will look at how to minimize power consumption in commonly used embedded processor (I/O) peripherals. Later we will talk about the various algorithmic techniques for power management.

On the first topic, things to consider include the peripheral’s burst size, speed grade, transfer width, and general communication modes. The main standard forms of peripheral communication for embedded processors include DMA (direct memory access), SRIO (serial rapid I/O), Ethernet, PCI Express, and RF antenna interfaces. I2C and UART are also commonly used, though mostly for initialization and debug purposes.

Tags: Embedded, Software,
Parlament, London

Parlament,
London, United Kingdom

ADN Editor in Chief
Dr Toomas P Plaks

London
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