ADN Issue 10, September 2014


the end

More News from World

Open Interconnect Consortium and Hypercat collaborate on IoT interoperability
Atmel, September 2, 2014

The UK Government’s Hypercat standard is collaborating with the Open Interconnect Consortium (OIC) to develop and ensure the interoperability of the 212 billion devices projected to be connected to the Internet by 2020, CBR reports.

Hypercat, which is comprised of 40 UK-based tech firms including IBM, ARM and BT, is a specification that allows applications to ask data hubs what types of data it holds and what permission it needs to ask them, making sense of it without human involvement. It can browse machines, searches by metadata and uses standards such as HTTPS, Restful APIs and JSON as a data format.

Tags: Internet of Things,
A map of every connected device on Earth
Atmel, September 2, 2014

As the saying goes, a picture is worth a thousand words, or in this case, billions of things. John Matherly, Founder of Shodan, recently created a map depicting the location of every single Internet-connected device across the globe. In order to achieve this feat, the creator pinged every device online, then mapped the location of the ones that responded.

Tags: Internet-Connected Devices, Internet of Things,
The secret world of submarine cables
Sebastian Anthony
ExtremeTech, September 21, 2011

The internet’s largest and most important — and yet unsung — champions are the privately-owned submarine cables that orbit the Earth. Terra firma links between cities and cables that run alongside roads and into houses and officers are certainly impressive — and without them we wouldn’t have an internet! — but sinking a cable into the Pacific, Atlantic, Indian, and even Arctic Oceans requires a billion-dollar logistical feat that requires months or even years to enact.

Tags: Networks, Internet,
Intilop Releases 16K Concurrent-TCP-Session Hardware Accelerator Verified and Tested on Xilinx Virtex-7 FPGA VC707 Evaluation Kit
MarketWatch, July 17, 2014

Intilop, Inc. a pioneer, most respected and recognized leader in providing Ultra-Low latency and Hyper Performance Complex Networking Protocol Accelerators, Mega IP Cores, Systems and Solutions, has released a 16K concurrent-TCP-session Hardware Accelerator Verified on a Virtex®-7 FPGA VC707 Evaluation Kit This deployment ready with pre-ported and verified 10G TCP Accelerator (TCP Full Offload Engines) that implement from 2 to 16 Thousand Simultaneous TCP Connections, unlimited continuous connections and Bandwidth of more than 1.1 Gigabyte/sec per port regardless of number of simultaneous or active TCP Sessions.

The FPGA platform offers an ‘Out of the box’ working TCP hardware stacks with unprecedented functionality, ultra small core size, high performance and flexibility. The Full TCP core runs without any CPU involvement through all stages of TCP transactions, including connection set up, data transfer, tcp-retries and connection tear down. The TCP connections maintain the same high throughput and low latency/processing times regardless of number of simultaneous connections in progress.

Tags: FPGA, CPU, Cloud-Computing, Security, Networks,
Performance Comparison Between Intel(r) Mobile-Class and Server-Class Processors for Embedded Defense Applications
Mercury Systems
Embedded Computing Design, June 19, 2014

Mercury continually evaluates new processors to better understand their performance and applicability for defense embedded applications. In this paper, we’ve highlighted the results from our recent tests comparing Intel(r) mobile-class versus server-class processors.

  • Server-class processors provide a 2-3X performance gain
  • Leveraging SMP delivers performance benefits
  • These combined performance gains can also provide SWaP advantages, as one server-based board can replace up to three mobile-class boards

These results point to the Intel server-class processor being a viable device for embedded applications that require high performance. Mercury has designed products based on both server- and mobile-class processors to best meet the specific needs of our customers.

Tags: Embedded, Defense, Application,
Multi-Core FFT Performance on Intel(r) Sandy Bridge Processors
Mercury Systems
Embedded Computing Design, June 19, 2014

This paper examines scalability of computational performance with the Intel(r) Sandy Bridge multicore architecture, particularly when used on Mercury processor boards.

We look specifically at two device types, an 8-core Xeon (E5-2648L clocked at 1.8 GHz) and a 4-core Core i7 (2715QE clocked at 2.1 GHz). These are relatively low-power devices which are suitable for use on embedded processor boards. The algorithm of interest is a complex FFT (fft_copx) from the Mercury MathPack library, which represents the numerically intensive processing requirements typical of many embedded signal processing systems. One question to be addressed is whether there is a falloff in performance as the FFT algorithm is run on one or more cores of the same device simultaneously. Even though the cores are independent and have their own L1 and L2 cache, they share access to an L3 cache and to the DRAM memory controller. As the FFT size increases from 1K (1024 points) to 1M (1,048,576 points), demands on the memory subsystem increase as the cores compete for this limited resource.

This means that for some applications, you cannot simply measure the timing on a single core, and then scale the results to size your system - the falloff in performance as all cores are utilized must be taken into account.

Tags: Multicore, Embedded, Compute-Intensive,
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