Here is a list of most visited and downloaded ERSA-ADN papers.
No particular order
J.P. Morrison Enterprises Ltd., Unionville, Ontario, Canada
ADN Issue 1, Mar 2013
In this paper, we give a short description of an application development technology
called Flow-Based Programming (FBP), briefly describing its basic concepts, history,
and some of our experience with it. An early implementation of FBP has been in continuous
production use for almost 40 years, but it is attracting attention world-wide as
it is a significant and important paradigm in building and maintaining computer applications.
Reconfigurable and Evolvable Architectures and their role in Designing Computational Systems
The University of York, UK
Biological inspiration in the design of computing machines finds its source in essentially
three biological models: phylogenesis, the history of the evolution of the species, ontogenesis,
the development of an individual as directed by his genetic code, and epigenesis, the development
of an individual through learning processes influenced both by their genetic code and by the environment.
These three models share a common basis: a one-dimensional description of the organism, the genome.
If one would like to implement some or all of these ideas in hardware can we use COTS or do we need
specifically designed-for-purpose devices?
Software-Based Reconfigurable Computing Platform (AppSTARTM) for Multi-Mission Payloads in
Spaceborne and Near-Space Vehicles
Harris Corporation, USA
We present an on-demand rapidly reconfigurable (~seconds) software-defined payload (SDP)
architecture called AppSTARTM with a core in-situ re-programmable processing capability that
supports communications, radar, signal analysis and other missions. At the heart of Harris‘
AppSTARTM SDP concept is a Virtex-based FPGA and interconnect fabric architecture that provides
for a modular, flexible, scalable core capable of supporting a broad spectrum of missions with
capabilities that can be customized for size, weight and power (SWaP) challenged platforms.
Illustrating some of the capabilities evolving from this work, we present two real-world space
qualified/qualifable SDPs, 1) a 100 Mbps-capable Ka-band software defined radio (SDR) for NASA and 2)
a space-ready SAR/ISAR X-band RADAR based on the AppSTARTM core.
From Streaming Models to FPGA Implementations
National Instruments Corporation, USA
Application advances in the signal processing and communications domains are marked
by an increasing demand for better performance and faster time to market. This has motivated
model-based approaches to design and deploy such applications productively across diverse
target platforms. Dataflow models are effective in capturing these applications that are
real-time, multi-rate, and streaming in nature. These models facilitate static analysis of
key execution properties like buffer sizes and throughput. There are established tools to
generate implementations of these models in software for processor targets. However, prototyping
and deployment on hardware targets, such as FPGAs, are critical to the development of new
applications. FPGAs are increasingly used in computing platforms for high performance streaming applications.
How Parameterizable Run-time FPGA- Reconfiguration can Benefit Adaptive Embedded Systems
Ghent University, Belgium
In this presentation, we assume that runtime adaptive embedded systems have proven benefits
over static implementations and we ask ourselves how such an adaptive system could be implemented.
It is clear that the system adaptation should be done very fast so that the overhead of adapting the
system does not overshadow the benefits obtained by the adaptivity. In this presentation, we propose
a methodology for FPGA design that allows a fast reconfiguration for dynamic datafolding applications.
Dynamic Data Folding (DDF) is a technique to dynamically specialize an FPGA configuration according to
the values of a set of parameters. The general idea of DDF is that each time the parameter values change,
the device is reconfigured with a configuration that is specialized for the new parameter values.
How Engineering Mathematics can Improve Software
Middle Road Software, Inc, Canada
For many decades we have been promised that the “Formal Methods” developed by computer scientists
would bring about a drastic improvement in the quality and cost of software development. That improvement
has not materialized. We review the reasons for this failure. We then explain the difference between the
notations that are used in formal methods and the mathematics that is essential in other areas of Engineering.
Finally, we illustrate the way that Engineering Mathematics has proven useful in a variety of software projects.
Ensuring Design Integrity through Analysis of FPGA Bitstreams and IP Cores
Luna Innovations Inc., USA
In this paper, we introduce a novel, broad definition of field programmable gate array (FPGA)
design integrity and explore its value in the domains of Trust, high-reliability design, and design
anti-obsolescence for FPGA-based systems. We claim that an FPGA design with integrity must continuously
provide the FPGA user with the function described by the designer and no other function. A common
starting point for approaching design integrity in each of the explored domains is the FPGA bitstream.
Luna’s unique software that evaluates the previously inaccessible designs inside of these bitstreams
and third-party intellectual property (IP) provides a firm foundation for analysis of FPGA design integrity.
Elliptic curve cryptography on FPGAs: How fast can we go with a single chip?
Aalto University, Finland
This work presents a highly optimized FPGA-based implementation of elliptic curve cryptography.
The work relies on the state-of-the-art algorithms and implementation techniques. Contrary to many
other published elliptic curve processors, the implementation fully utilizes the possibilities offered
by reconfigurability by optimizing all hierarchical levels of elliptic curve operations for a specific
elliptic curve and parameters which ensures the best possible performance. Support for other curves and
parameters is achieved through reconfiguration. The results of the work show that one modern FPGA chip
is capable of performing over 1,000,000 scalar multiplications per second on a standardized 163-bit elliptic curve.
Towards OpenCL Compilation into High-Performance Hardware for FPGAs
University of Toronto & Altera, Canada
Hardware acceleration using FPGAs has shown orders of
magnitude reduction in runtime of computationally-intensive
applications in comparison to traditional stand-alone computers .
This is possible because on an FPGA many computations can be performed at the same time in a truly-
parallel fashion. However, parallel computation at a hardware level requires a great
deal of expertise, which limits the
adoption of FPGA-based acceleration platform.