Call for Papers
Special Issue on
Configuring Algorithms, Processes and Architecture
Embedded computing systems have become an essential part of modern life. Mobile phones are now handheld multimedia computers; automotive industry needs hundreds of embedded processors to build a modern car; around us are smart sensor systems for monitoring, security and healthcare, if to mention some them. There is estimation that in the near future, in 2010, about 90% of computer applications are embedded systems, most of these are mobile, wireless consumer appliances that must be small in size, with very low power consumption and with high performance.
Advances in microelectronics have changed the technology. It is now essential that one die contains several processor cores. In a near future hundreds and thousands of simple processor cores are replacing complex processors on a single chip, forming a high-performance multiprocessor. This has changed the design concepts of microelectronic devices, the design concepts of embedded application-specific processors. Reconfigurable computing using field programmable gate arrays (FPGAs) have been long time widely used in embedded digital system design. Now, the reconfiguring is migrating from the circuit level to the level of simple processors and algorithms. The hot topic in dedicated processor design is not anymore logic, digital design, it is now more reconfigurable multiprocessing.
Configurable parallel processing has many advantages. First, it replaces time-consuming digital design by programming of multiprocessors, reducing, thus, the design cost and time, and, makes the design reprogrammable. Second, algorithms are mapped directly onto configurable space of simple processors achieving the efficiency of Application-Specific Integrated Circuits (ASICs). Third, the multiprocessor concept facilitates the building of energy efficient systems using dynamic shutdown of unused processors. And last, the performance is scalable and depends on the algorithmic design, on the number of processors involved and not on the clock frequency of electrical circuits.
Efficient mapping of algorithms onto hardware requires simultaneous study of algorithms and architecture: The algorithm must fit the architecture and the architecture must fit the algorithm. To achieve a best match, one has to be able to (re)configure the architecture as well the algorithms. Coupling this with the multiprocessing requirements where several computational processes are running on the same computational space (forming from elementary processors and connections) and competing for computational resources (processors and connections), the sophisticated system with dynamic reconfiguration controlled by an operating system is formed.
Thus, a new scenario of hardware/software Codesign has been formed. Dealing with this new scenario, the gap between hardware and software is rather small. Configurable computing introduces traditional software related topics as languages, operating systems, and integrates these with hardware related topics of digital design. While in general, there is a similarity in theoretical models and methods on the functional level, the actual methods involved are rather different and need much specific attention from researchers.
This special issue focuses on the different approaches in engineering of reconfigurable systems and implementing of algorithms, including theory, architecture, algorithms, design systems and applications that demonstrate the benefits of reconfigurable computing.
Topics of interest include but are not limited to:
- Theory - Synthesis, Mapping, Parallelization, Partitioning...
- Software - CAD, Languages, Compilers, Operating Systems...
- Hardware - Adaptive and Dynamic Hardware, Reconfigurable Architectures...
- Applications - Mobile Computing, Automotive Industry, Smart Cameras...
A selected number of top papers from ERSA’2009 are invited by the guest editor for review. Authors of these papers are asked to extend their work for a TECS journal publication, which is then subjected to rigorous review process. Besides submissions from ERSA’09 any other high quality submissions that fits the topics of the special issues are welcome. Authors should submit their journal version at Manuscript Central adhering to the formatting instructions on the TECS Web page and indicate that you are submitting to the Special Issue on Configurable Computing: Configuring Algorithms, Processes and Architecture (on the first page and in the field "Author's Cover Letter:" in manuscriptcentral). For additional questions please Contact. Page limit: 25 pages.
|Submission deadline (extended):||June 30, 2009|
|Review results:||approx. Nov. 15, 2009|
|Final copy deadline:||approx. January 15, 2010|
Please note: disclosure of review results and the final copy deadline may defer.
Dr. Toomas P. Plaks, Conhard Design Ltd and Reading Univ, UK
Associate Guest Editors:
Prof. Ronald F. DeMara, Univ. of Central Florida, USA
- Prof. Xinming Huang, Worcester Polytechnic Institute, USA
- Prof. Jack Jean, Wright State Univ., USA
Prof. Cameron Patterson, Virginia Tech., USA
Prof. Mario Porrmann, Univ. of Paderborn, Germany