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ERSA’14

July 21 -- 24, 2014

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IEEE TVLSI Special Section on
Configurable Computing Design

Issue 2: Hardware Level Reconfiguration

IEEE TVLSI Volume: 16 Issue: 2 Date: Feb. 2008
  • Guest Editorial Special Section on Configurable Computing Design II: Hardware Level Reconfiguration
    Plaks, T. P.
    Page(s): 113-114

  • A Low-Power Reconfigurable Logic Array Based on Double-Gate Transistors
    Beckett, P.
    Page(s): 115-123
    Abstract

  • Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs
    Lin, Y.; He, L.; Hutton, M.
    Page(s): 124-133
    Abstract

  • Applying Dynamic Reconfiguration for Fault Tolerance in Fine-Grained Logic Arrays
    Zipf, P.
    Page(s): 134-143
    Abstract

  • Reconfigurable Hardware for High-Security/ High-Performance Embedded Systems: The SAFES Perspective
    Gogniat, G.; Wolf, T.; Burleson, W.; Diguet, J.-P.; Bossuet, L.; Vaslin, R.
    Page(s): 144-155
    Abstract

  • Scalable Multigigabit Pattern Matching for Packet Inspection
    Sourdis, I.; Pnevmatikatos, D. N.; Vassiliadis, S.
    Page(s): 156-166
    Abstract

  • Area-Efficient Arithmetic Expression Evaluation Using Deeply Pipelined Floating-Point Cores
    Scrofano, R.; Zhuo, L.; Prasanna, V. K.
    Page(s): 167-176
    Abstract

  • Architectural Modifications to Enhance the Floating-Point Performance of FPGAs
    Beauchamp, M. J.; Hauck, S.; Underwood, K. D.; Hemmert, K. S.
    Page(s): 177-187
    Abstract

  • System Architecture and Implementation of MIMO Sphere Decoders on FPGA
    Huang, X.; Liang, C.; Ma, J.
    Page(s): 188-197
    Abstract


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Luxor

LUXOR
Reconfigurable Las Vegas

Conference Chair
Dr Toomas P Plaks

London
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