July 21 -- 24, 2014

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ACM TECS CAPA’09 Special Issue

Configurable Computing:
Configuring Algorithms, Processes and Architecture

Guest Editor: Dr Toomas P Plaks, London, UK

Associate Guest Editors:
Prof. Ronald F. DeMara, Univ. of Central Florida, USA
Prof. Jack Jean, Wright State Univ., USA
Prof. Cameron Patterson, Virginia Tech., USA
Prof. Mario Porrmann, Univ. of Paderborn, Germany

List of accepted papers

  • Hierarchical Benchmark Circuit Generation for FPGA Architecture Evaluation
    Cindy Mark*, Lesley Shannon**, Steven J.E. Wilton*
    *University of British Columbia, Canada; **Simon Fraser University, Canada


    We describe a stochastic circuit generator that can be used to automatically create benchmark circuits for use in FPGA architecture studies. The circuits consist of a hierarchy of interconnected modules, reflecting the structure of circuits designed using a system-on-chip design flow. Within each level of hierarchy, modules can be connected in a bus, star, or dataflow configuration. Our circuit generator is calibrated based on a careful study of existing system-on-chip circuits. We show that our benchmark circuits lead to more realistic architectural conclusions than circuits generated using previous generators.

  • RapidRadio: Signal Classification and Radio Deployment Framework
    Jorge A. Suris, Adolfo Recio, Peter Athanas
    Virginia Polytechnic Institute and State University, USA


    The RapidRadio framework is a productivity enhancing tool that reduces the required knowledge-base for implementing a receiver on an FPGA-based SDR platform. The objective of this framework is to identify unknown signals and to build FPGA-based receivers capable of receiving them. RapidRadio divides the process of radio creation into two phases; the analysis phase and radio synthesis phase. The analysis phase guides the user through the process of classifying a signal and determining its modulation scheme and parameters, resulting in a radio receiver model. In the second phase, this model is transformed into a functional receiver in an FPGA-based platform.

  • RCML: An Environment for Estimation Modeling of Reconfigurable Computing Systems
    Casey Reardon, Brian Holland, Alan D. George, Greg Stitt, Herman Lam
    NSF Center for High-performance Reconfigurable Computing (CHREC), University of Florida, Gainesville, FL, USA


    Reconfigurable computing (RC) is emerging as a promising field for embedded computing, where complex systems must balance performance, flexibility, cost, and power consumption. The difficulty associated with RC development suggests improved strategic planning and analysis techniques can save designers significant development time and effort. This article presents an abstract modeling environment called the RC Modeling Language (RCML) to facilitate efficient design-space exploration of RC systems at the estimation modeling level, i.e. before building a functional implementation. Two integrated analysis tools and case studies, one analytical and one simulative, are presented illustrating relatively accurate automated analysis of systems modeled in RCML.

  • Architecture Optimization of Dynamically Configured Application-Specific Implicit Instructions
    Giovanni Agosta, Andrea Di Biagio, Cristina Silvano, Martino Sykora
    Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy


    Dynamic configuration of application specific implicit instructions has been proposed to better exploit the available parallelism in pipelined processors. This requires the pipeline to be extended with a trigger table that describes the instruction implicitly issued as a response to a value written into a triggering register. In this paper, we explore the design optimization of the trigger table to maximize the number of instructions that can be implicitly issued while keeping limited the size of the trigger table. The proposed solutions have been applied to the case of a baseline scalar MIPS processor obtaining an average speedup of 17%.

  • Multi-Core Reconfigurable Computing for Advanced Video Coding
    Anand Paul, Yung-Chuan Jiang, Jhing-Fa Wang, Jar-Ferr Yang
    National Cheng Kung University, Department Of Electrical Engineering, Tainan,Taiwan


    Computational load of motion estimation in advanced video coding standard is significantly high and even worse for HDTV and super-resolution sequences. In this paper, video processing algorithm is dynamically mapped onto a new parallel reconfigurable computing (PRC) architecture, which consists of multiple dynamic reconfigurable computing (DRC) units. We construct a directed acyclic graph (DAG) to represent video coding algorithms, in which motion estimation is focused. A novel parallel partition approach is then proposed to map motion estimation DAG onto the multiple DRC units in a PRC system. This speeds up the video processing with minimum sacrifice.

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